US6046624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Internal power supply generating circuit for a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-12-10
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Granted: 2000-04-04
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Expires: 2017-12-10
Abstract
Abstract An internal power supply generating circuit for a semiconductor memory device reduces fluctuations in the external power supply by reducing the rate at which a drive transistor is turned on and off. The circuit includes a drive transistor that generates an internal power signal by reducing the external power supply voltage responsive to a bias signal. A feedback loop generates the bias signal and slows down the rate at which the bias signal changes, thereby reducing the rate at which the drive transistor turns on and off. The feedback loop includes a comparator for comparing the internal power supply voltage to a reference voltage and a bias circuit having a pair of push-pull transistors for generating the bias signal responsive to the output of the comparator. To slow down the rate at which the bias signal changes, the bias circuit includes a resistor coupled in series with the transistors and/or a capacitor couple to the output terminal of the bias circuit. Alternatively, the bias circuit includes a third transistor coupled in series with the push-pull transistors. A voltage divider is coupled to the gate of the third transistor and the gate of one of the push-pull transistors to turn the third transistor on. The feedback loop optionally includes a delay circuit to prevent malfunctions caused by the differences in voltage associated with sensing the internal power supply voltage at remote locations on a memory device.
Inventors
- 👤 Ga-Pyo Nam
- 👤 Yong-sik Seok
- 👤 Hi-choon Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:25
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
267 words
An internal power signal generating circuit for a semiconductor memory device comprising: a driver for reducing the voltage of an external power signal responsive to a bias signal, thereby generating an internal power signal, the driver having an input terminal for receiving the bias signal, a power terminal for receiving the external power signal, and an output terminal for transmitting the internal power signal; and a feedback loop coupled to the driver for generating the bias signal responsive to the internal power signal and a reference signal; wherein the feedback loop reduces the rate at which the bias signal changes; wherein the feedback loop includes: a comparator having a first input terminal coupled to the output terminal of the driver to receive the internal power signal, a second input terminal coupled to receive a reference signal, and an output terminal for transmitting a comparison signal; and a bias circuit having an input terminal coupled to the output terminal of the comparator for receiving the comparison signal, and an output node coupled to the input terminal of the driver; and wherein the bias circuit includes: a pair of transistors arranged in a push-pull configuration to generate the bias signal, each transistor having an input terminal coupled to receive the comparison signal and an output terminal coupled to the output node of the bias circuit; a third transistor coupled in series with the pair of transistors; and a voltage divider having an input terminal coupled to the input terminal of one of the pair of transistors and an output terminal coupled to an input terminal of the third transistor.
Claim 2
Dependent Claim
267 words
An internal power signal generating circuit for a semiconductor memory device comprising: a driver for reducing the voltage of an external power signal responsive to a bias signal, thereby generating an internal power signal, the driver having an input terminal for receiving the bias signal, a power terminal for receiving the external power signal, and an output terminal for transmitting the internal power signal; and a feedback loop coupled to the driver for generating the bias signal responsive to the internal power signal and a reference signal; wherein the feedback loop reduces the rate at which the bias signal changes; wherein the feedback loop includes: a comparator having a first input terminal coupled to the output terminal of the driver to receive the internal power signal, a second input terminal coupled to receive a reference signal, and an output terminal for transmitting a comparison signal; and a bias circuit having an input terminal coupled to the output terminal of the comparator for receiving the comparison signal, and an output node coupled to the input terminal of the driver; and wherein the bias circuit includes: a pair of transistors arranged in a push-pull configuration to generate the bias signal, each transistor having an input terminal coupled to receive the comparison signal and an output terminal coupled to the output node of the bias circuit; a third transistor coupled in series with the pair of transistors; and a voltage divider having an input terminal coupled to the input terminal of one of the pair of transistors and an output terminal coupled to an input terminal of the third transistor.
Claim 3
Dependent Claim
270 words
An internal power supply generating circuit for a semiconductor memory device comprising: a comparator for comparing an internal power supply voltage with a predetermined reference voltage; a delay logic circuit coupled to the comparator for delaying an output signal from the comparator; a bias portion coupled to the delay logic circuit for responding to an output signal from the delay logic circuit; and a driver coupled to the bias portion for driving the internal power supply when the internal power supply voltage is lower than the reference voltage; wherein the bias portion comprises: first inverting means for inverting the output signal from the delay logic circuit; second inverting means for inverting the output signal from the delay logic circuit; a resistor having a first node connected to an external power supply; a pull-up transistor having a source connected to a second node of the resistor and a gate coupled to the comparator to turn the pull-up transistor on when the internal power supply voltage is higher than the reference voltage; a first pull-down transistor having a source connected to a power supply ground, and a gate coupled to the comparator to turn the pull-down transistor on when the internal power supply voltage is lower than the reference voltage; a voltage divider for generating a predetermined voltage in response to the output signal of the first inverting means or the output signal of the second inverting means; and a second pull-down transistor having a gate connected to an output terminal of the voltage divider, a source connected to ground and a drain connected to a source of the first pull-down transistor.
Claim 4
Dependent Claim
270 words
An internal power supply generating circuit for a semiconductor memory device comprising: a comparator for comparing an internal power supply voltage with a predetermined reference voltage; a delay logic circuit coupled to the comparator for delaying an output signal from the comparator; a bias portion coupled to the delay logic circuit for responding to an output signal from the delay logic circuit; and a driver coupled to the bias portion for driving the internal power supply when the internal power supply voltage is lower than the reference voltage; wherein the bias portion comprises: first inverting means for inverting the output signal from the delay logic circuit; second inverting means for inverting the output signal from the delay logic circuit; a resistor having a first node connected to an external power supply; a pull-up transistor having a source connected to a second node of the resistor and a gate coupled to the comparator to turn the pull-up transistor on when the internal power supply voltage is higher than the reference voltage; a first pull-down transistor having a source connected to a power supply ground, and a gate coupled to the comparator to turn the pull-down transistor on when the internal power supply voltage is lower than the reference voltage; a voltage divider for generating a predetermined voltage in response to the output signal of the first inverting means or the output signal of the second inverting means; and a second pull-down transistor having a gate connected to an output terminal of the voltage divider, a source connected to ground and a drain connected to a source of the first pull-down transistor.
Claim 5
Dependent Claim
85 words
The internal power supply generating circuit of claim 2, wherein the voltage divider comprises: a PMOS transistor having a source connected to the external power supply and a gate connected to ground; a first NMOS transistor having a gate connected to an input of the voltage divider and a drain commonly connected to the drain of the PMOS transistor; and a second NMOS transistor having a source connected to ground and a gate and drain commonly connected to the source of the first NMOS transistor.
Claim 6
Dependent Claim
31 words
The internal power supply generating circuit of claim 2, wherein the bias portion further comprises: a capacitor connected between an output node of the bias portion and a power supply terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-04 | 2003-10-04 | 2004-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-04 | 2007-10-04 | 2008-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-04 | 2011-10-04 | 2012-04-04 | $7700.00 | Window Closed / Lapsed |