US5561385A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Internal voltage generator for semiconductor device
Assignee: SK Hynix Inc
•
Filing: 1995-04-10
•
Granted: 1996-10-01
•
Expires: 2015-04-10
Abstract
Abstract An internal voltage generator for a semiconductor device, for generating an internal voltage within the device which may include: a charge pump generating a DC voltage by rectifying clock signals; a variable frequency oscillator generating variable oscillation frequency clock signals in accordance with control signals; and a voltage control means detecting the level of a voltage maintained by the output voltage of the charge pump so as to generate control signals for controlling the variable frequency oscillator.
Inventors
- 👤 Go-Hee Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:32
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/354; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; H03K3/027; H03K3/03
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
206 words
A voltage generator for generating an internal voltage of a desired level on a terminal in a semiconductor device, comprising: a charge pump coupled to the terminal and generating a voltage by rectifying clock signals; a variable frequency oscillator coupled to the charge pump and providing variable oscillation frequency clock signals to the charge pump in accordance with one or more control signals; and a voltage control means for detecting the level of voltage maintained on the terminal and generating control signals for controlling the frequency of the variable frequency oscillator; wherein the voltage control means comprises: a voltage level detector generating a signal voltage in response to detecting the difference between a reference voltage level and the internal voltage; and an oscillation control section receiving the signal voltage of the voltage level detector and generating the one or more control signals in the form of a current flowing in accordance with the magnitude of the signal voltage; and wherein the oscillation control section comprises:, an MOS transistor receiving the signal voltage into the gate of the MOS transistor, wherein a voltage detecting current flows in response to the voltage detecting current; and a current mirror generating a control current proportionately to the voltage detecting current.
Claim 2
Dependent Claim
206 words
A voltage generator for generating an internal voltage of a desired level on a terminal in a semiconductor device, comprising: a charge pump coupled to the terminal and generating a voltage by rectifying clock signals; a variable frequency oscillator coupled to the charge pump and providing variable oscillation frequency clock signals to the charge pump in accordance with one or more control signals; and a voltage control means for detecting the level of voltage maintained on the terminal and generating control signals for controlling the frequency of the variable frequency oscillator; wherein the voltage control means comprises: a voltage level detector generating a signal voltage in response to detecting the difference between a reference voltage level and the internal voltage; and an oscillation control section receiving the signal voltage of the voltage level detector and generating the one or more control signals in the form of a current flowing in accordance with the magnitude of the signal voltage; and wherein the oscillation control section comprises:, an MOS transistor receiving the signal voltage into the gate of the MOS transistor, wherein a voltage detecting current flows in response to the voltage detecting current; and a current mirror generating a control current proportionately to the voltage detecting current.
Claim 3
Dependent Claim
65 words
The generator of claim 1, wherein the variable frequency oscillator comprises: an oscillator comprising an odd number of inverting devices; and a power control means for controlling the supply of power from a power source to the inverting devices in accordance with the one or more control signals, whereby the oscillation frequency of the clock signals is controlled by the one or more control signals.
Claim 4
Dependent Claim
27 words
The generator of claim 2, wherein the oscillation frequency of the clock signals is controlled in an approximately linear manner by the one or more control signals.
Claim 5
Dependent Claim
60 words
The generator of claim 2, wherein the power control means is characterized in that an nMOS transistor is disposed between the inverting devices and the power source, wherein the current supplied to the inverting devices is controlled by the gate voltage of the MOS transistor, wherein the gate voltage of the MOS transistor varies in response to the control signals.
Claim 6
Dependent Claim
73 words
The generator of claim 4, wherein: the inverting devices comprise inverters consisting of series-connected pMOS transistors and nMOS transistors; and the power control means comprises a pMOS transistor between the power source and the pMOS transistors of the inverters, and an nMOS transistor disposed between a reference terminal and the nMOS transistors of the inverters; wherein the control signals are supplied to the gates of the respective transistors of the power control means.
Claim 7
Dependent Claim
52 words
The generator of claim 1, wherein the current mirror comprises: a first current mirror receiving the voltage detecting current and generating the control current in accordance with the voltage detecting current; and a second current mirror receiving the control current and generating a voltage controlling the oscillation frequency of the clock signals.
Claim 8
Dependent Claim
23 words
The generator of claim 6, wherein the first current mirror comprises two pMOS transistors, and the second current mirror comprises two nMOS transistors.
Claim 9
Dependent Claim
20 words
The generator of claim 1, wherein a driving circuit is coupled between the variable frequency oscillator and the charge pump.
Claim 10
Dependent Claim
25 words
The generator of claim 8, wherein the driving circuit comprises a buffer, wherein a current limiter is disposed between the buffer and the power source.
Claim 11
Dependent Claim
22 words
The generator of claim 9, wherein the current limiter comprises an MOS transistor receiving a control signal from the voltage control means.
Claim 12
Dependent Claim
46 words
The generator of claim 1, wherein the voltage level detector comprises a plurality of PMOS transistors and a plurality of nMOS transistors connected in series, wherein a first pMOS transistor is coupled to the power source, and a last nMOS transistor is coupled to the terminal.
Claim 13
Dependent Claim
202 words
A voltage generator for generating an internal voltage of a desired level on a terminal in a semiconductor device, comprising: a charge pump coupled to the terminal and generating a voltage by rectifying clock signals; a variable frequency oscillator coupled to the charge pump and providing variable oscillation frequency clock signals to the charge pump in accordance with one or more control signals; and a voltage control means for detecting the level of voltage maintained on the terminal and generating control signals for controlling the frequency of the variable frequency oscillator; wherein the variable frequency oscillator comprises: a first series of an odd number of inverting devices, wherein the output of a last inverting device of the first series is coupled to a set input of a flip-flop, and the input of a first inverting device of the first series is coupled to a first output of the flip-flop; and a second series of an odd number of inverting devices, wherein the output of a last inverting device of the second series is coupled to a reset input of the flip-flop, and the input of a first inverting device of the second series is coupled to a second output of the flip-flop.
Claim 14
Dependent Claim
202 words
A voltage generator for generating an internal voltage of a desired level on a terminal in a semiconductor device, comprising: a charge pump coupled to the terminal and generating a voltage by rectifying clock signals; a variable frequency oscillator coupled to the charge pump and providing variable oscillation frequency clock signals to the charge pump in accordance with one or more control signals; and a voltage control means for detecting the level of voltage maintained on the terminal and generating control signals for controlling the frequency of the variable frequency oscillator; wherein the variable frequency oscillator comprises: a first series of an odd number of inverting devices, wherein the output of a last inverting device of the first series is coupled to a set input of a flip-flop, and the input of a first inverting device of the first series is coupled to a first output of the flip-flop; and a second series of an odd number of inverting devices, wherein the output of a last inverting device of the second series is coupled to a reset input of the flip-flop, and the input of a first inverting device of the second series is coupled to a second output of the flip-flop.
Claim 15
Dependent Claim
64 words
The generator of claim 12, wherein the power source is applied to at least a first inverting device in a controlled manner, wherein a capacitor is coupled between the output of the inverting device and a reference potential, wherein the oscillation frequency of the clock signals varies in accordance with the capacitance of the capacitor and with the power applied by the power supply.
Claim 16
Dependent Claim
23 words
The generator of claim 13, wherein the inverting device is an inverter comprising a pMOS transistor and an nMOS transistor connected in series.
Claim 17
Dependent Claim
72 words
The generator of claim 13, wherein the voltage control means comprises: a voltage level detector generating a signal voltage in response to detecting the difference between a reference voltage level and the internal voltage; and an oscillation control section receiving the signal voltage from the voltage level detector and generating the one or more control signals in the form of a current flowing in accordance with the magnitude of the signal voltage.
Claim 18
Dependent Claim
52 words
The generator of claim 15, wherein the oscillation control section, comprise: an MOS transistor receiving the signal voltage into the gate of the MOS transistor, wherein a voltage detecting current flows in response to the voltage detecting current; and a current mirror generating a control current proportionately to the voltage detecting current.
Claim 19
Dependent Claim
13 words
The generator of claim 16, wherein the current mirror comprises two pMOS transistors.
Claim 20
Dependent Claim
33 words
The generator of claim 12, wherein a driving circuit is coupled between the variable frequency oscillator and the charge pump, wherein the clock signals applied to the change pump comprise a rectangular wave.
Claim 21
Dependent Claim
47 words
The generator of claim 15, wherein the voltage level detector comprises a plurality of pMOS transistors and a plurality of nMOS transistors connected in series, and wherein a first pMOS transistor is coupled to the power source, and a last nMOS transistor is coupled to the terminal.
Claim 22
Dependent Claim
43 words
The generator of claim 13, wherein the inverting device to which the power source is applied in a controlled manner is the first inverting device, and the first inverting device receives a control current through the current mirror of the oscillation control section.
References Cited (Backward Citations)
US4547682A
Cited
US4775959A
Cited
US4964082A
Cited
US4656369A
Cited
US4794278A
Cited
US4985869A
Cited
US5034625A
Cited
US5034625B1
Cited
US5003197A
Cited
US5426334A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |