US4985869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device with an improved substrate back-bias arrangement
Assignee: Hitachi Ltd
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Filing: 1989-07-05
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Granted: 1991-01-15
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Expires: 2009-07-05
Abstract
Abstract A substrate back bias voltage generator of a dynamic type RAM is provided with a first voltage generator having a relatively large current supply capacity, a second voltage generator having a relatively small current supply capacity, and a substrate back bias voltage detecting circuit for controlling operation of the first voltage generator. For example, when the dynamic type RAM is in a CAS before RAS refresh mode, the operation of the first voltage generator is limited selectively, and the operation of the second voltage generator and the substrate back bias voltage detecting circuit is stopped selectively.
Inventors
- 👤 Eiji Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:46
CPC Classifications
G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
A semiconductor memory device having a normal operation mode and refresh mode comprising: a first external terminal for receiving a row address strobe signal (RAS); a second external terminal for receiving a column address strobe signal (CAS); a first control means coupled to said first and second external terminals for initiating said refresh mode in response to said column address strobe signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge; a first back-bias voltage generation means coupled to a substrate of said semiconductor memory device for biasing said substrate with a first current supply capacity; a second back-bias voltage generation means coupled to said substrate for biasing said substrate with a second current supply capacity; a second control means coupled to said first control means and to said first and second back-bias voltage generation means for placing said first back-bias voltage generation means in an operation state in response to the first control means initiating said refresh mode during a predetermined time, and for placing said second back-bias voltage generation means in a non-operation state during said refresh mode.
Claim 2
Dependent Claim
194 words
A semiconductor memory device having a normal operation mode and refresh mode comprising: a first external terminal for receiving a row address strobe signal (RAS); a second external terminal for receiving a column address strobe signal (CAS); a first control means coupled to said first and second external terminals for initiating said refresh mode in response to said column address strobe signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge; a first back-bias voltage generation means coupled to a substrate of said semiconductor memory device for biasing said substrate with a first current supply capacity; a second back-bias voltage generation means coupled to said substrate for biasing said substrate with a second current supply capacity; a second control means coupled to said first control means and to said first and second back-bias voltage generation means for placing said first back-bias voltage generation means in an operation state in response to the first control means initiating said refresh mode during a predetermined time, and for placing said second back-bias voltage generation means in a non-operation state during said refresh mode.
Claim 3
Dependent Claim
40 words
A semiconductor memory device according to claim 1, further comprising a detection means for detecting a voltage level of said substrate, wherein said first back-bias voltage generation means is controlled on the basis of an output of said detection means.
Claim 4
Dependent Claim
27 words
A semiconductor memory device according to claim 2, further comprising a third control means for placing said detection means in a non-operation state during said refresh mode.
Claim 5
Dependent Claim
22 words
A semiconductor memory device according to claim 3, wherein said first current supply capacity is greater than said second current supply capacity.
Claim 6
Dependent Claim
34 words
A semiconductor memory device according to claim 4, wherein said first control means includes means for clearing said refresh mode in response to said row address strobe signal returning to a logic "high" level.
Claim 7
Dependent Claim
41 words
A semiconductor memory device according to claim 5, wherein said second control means includes means to place said first back-bias voltage generation means in an operation state in response to said row address strobe signal returning to a logic "high" level.
Claim 8
Dependent Claim
31 words
A semiconductor memory device according to claim 5, wherein a period of said operation state of said first back-bias voltage generation state is shorter than a period of said refresh mode.
References Cited (Backward Citations)
US4775959A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-14 | 1994-07-16 | 1995-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-14 | 1998-07-16 | 1999-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-14 | 2002-07-16 | 2003-01-15 | $7700.00 | Window Closed / Lapsed |