CMOS power-on reset circuit

Claim 1

A power-on circuit for generating a binary reset output signal having a valid state and an invalid state, comprising: input means for receiving and scaling a power supply voltage to be monitored; threshold voltage means for providing a threshold voltage; first comparator means for comparing the scaled power supply voltage to the threshold voltage and indicating a valid power supply state when the power supply voltage exceeds the threshold voltage and for indicating an invalid power supply state otherwise; a delay timer for providing a predetermined delay period and indicating completion of the delay period; the delay timer including: a delay capacitor; a current source for charging the delay capacitor; a first transistor switch disposed between the current source and the delay capacitor to control charging of the capacitor; a second transistor switch coupled to the capacitor for controllably discharging the capacitor; and a flip-flop having a Q output coupled to the first and second switches for charging and discharging the delay capacitor, respectively, in response to a current state of the flip-flop; means for starting the delay timer responsive to the indication of a valid power supply state; means for delaying said starting the delay timer until after the delay timer indicates completion of the delay period, to ensure that at least the delay period elapses since the power supply last becoming invalid before changing the reset output signal to the valid state; and means coupled to the first comparator means for forcing the reset output signal to an invalid state responsive to the indication of an invalid power supply state and without regard to the delay period, thereby immediately forcing the reset signal to the invalid state without delay and wherein said means for starting the delay timer include means for resetting the flip-flop thereby enabling the first transistor switch to begin charging the delay capacitor responsive to the indication of the invalid state; and and means for delaying said starting the delay timer include a voltage comparator having a first input coupled to the delay capacitor and a second input coupled to a reference voltage and an output coupled to logic means for resetting the flipflop only after the capacitor voltage crosses the reference voltage.

Claim 6

A method of generating a power-on reset signal responsive to a power supply input voltage comprising: initially asserting the reset signal in a predetermined invalid state; providing a threshold voltage having an initial value; comparing the input voltage to the threshold voltage; after at least a predetermined delay period has elapsed during which delay period the input voltage continuously exceeds the threshold voltage, switching the reset signal to a valid state; responsive to said switching step, lowering the threshold voltage; comparing the input voltage to the lowered threshold voltage, thereby permitting the input voltage to sag after initialization without switching the reset signal back to the invalid state; responsive to the input voltage falling below the lowered threshold voltage, immediately switching the reset signal back to the invalid state without delay; maintaining the reset signal in the invalid state for at least the delay period without regard to the input voltage level; and upon a conclusion of at least the delay period, restoring the threshold voltage to its initial value.

Claim 7

A method of generating a power-on reset signal responsive to a power supply input voltage comprising: initially asserting the reset signal in a predetermined invalid state; providing a threshold voltage having an initial value; comparing the input voltage to the threshold voltage; after at least a predetermined delay period has elapsed during which delay period the input voltage continuously exceeds the threshold voltage, switching the reset signal to a valid state; responsive to said switching step, lowering the threshold voltage; comparing the input voltage to the lowered threshold voltage, thereby permitting the input voltage to sag after initialization without switching the reset signal back to the invalid state; responsive to the input voltage falling below the lowered threshold voltage, immediately switching the reset signal back to the invalid state without delay; maintaining the reset signal in the invalid state for at least the delay period without regard to the input voltage level; and upon a conclusion of at least the delay period, restoring the threshold voltage to its initial value.

Claim 9

A method of generating a power-on reset signal responsive to a power supply input voltage comprising: initially asserting the reset signal in a predetermined invalid state; providing a threshold voltage having an initial value; comparing the input voltage to the threshold voltage; after at least a predetermined delay period has elapsed during which delay period the input voltage continuously exceeds the first threshold voltage, switching the reset signal to a valid state; responsive to said switching step, comparing the threshold voltage to a delay capacitor voltage to detect a conclusion of the delay period when the delay capacitor voltage exceeds the threshold voltage; and lowering the threshold voltage responsive to detecting the conclusion of the delay period and then comparing the input voltage to the lowered threshold voltage, thereby permitting the input voltage to sag after initialization without switching the reset signal back to the valid state.

Claim 10

A method of generating a power-on reset signal responsive to a power supply input voltage comprising: initially asserting the reset signal in a predetermined invalid state; providing a threshold voltage having an initial value; comparing the input voltage to the threshold voltage; after at least a predetermined delay period has elapsed during which delay period the input voltage continuously exceeds the first threshold voltage, switching the reset signal to a valid state; responsive to said switching step, comparing the threshold voltage to a delay capacitor voltage to detect a conclusion of the delay period when the delay capacitor voltage exceeds the threshold voltage; and lowering the threshold voltage responsive to detecting the conclusion of the delay period and then comparing the input voltage to the lowered threshold voltage, thereby permitting the input voltage to sag after initialization without switching the reset signal back to the valid state.

Claim 11

A method of generating a power-on reset signal responsive to a power supply input voltage comprising: initially asserting the reset signal in a predetermined invalid state; providing a threshold voltage having an initial value; comparing the input voltage to the threshold voltage; providing a delay capacitor; responsive to a invalid power supply input voltage, discharging the delay capacitor; continuously monitoring the delay capacitor voltage and indicating when the delay capacitor is substantially discharged; responsive to a valid input voltage, and only if the delay capacitor is substantially discharged, recharging the delay capacitor; comparing the delay capacitor voltage to the threshold voltage; responsive to an indication that the delay capacitor voltage exceeds the threshold voltage, so that at least a predetermined delay period has elapsed during which delay period the input voltage continuously exceeded the first threshold voltage, and only if the input voltage is valid, switching the reset signal to the valid state; responsive to said switching step, lowering the threshold voltage; and comparing the input voltage to the lowered threshold voltage, thereby permitting the input voltage to sag after initialization without switching the reset signal back to the invalid state.

Claim 12

A method of generating a power-on reset signal responsive to a power supply input voltage comprising: initially asserting the reset signal in a predetermined invalid state; providing a threshold voltage having an initial value; comparing the input voltage to the threshold voltage; providing a delay capacitor; responsive to a invalid power supply input voltage, discharging the delay capacitor; continuously monitoring the delay capacitor voltage and indicating when the delay capacitor is substantially discharged; responsive to a valid input voltage, and only if the delay capacitor is substantially discharged, recharging the delay capacitor; comparing the delay capacitor voltage to the threshold voltage; responsive to an indication that the delay capacitor voltage exceeds the threshold voltage, so that at least a predetermined delay period has elapsed during which delay period the input voltage continuously exceeded the first threshold voltage, and only if the input voltage is valid, switching the reset signal to the valid state; responsive to said switching step, lowering the threshold voltage; and comparing the input voltage to the lowered threshold voltage, thereby permitting the input voltage to sag after initialization without switching the reset signal back to the invalid state.

Claim 13

A method of generating a power-on reset signal in a CMOS integrated circuit responsive to a power supply input voltage comprising: providing first and second voltage comparators and a latch; in the first comparator, continuously comparing the power supply input voltage to a threshold voltage to form an indication that the input voltage is valid; in the second comparator, continuously monitoring a capacitor voltage to form an indication when the capacitor is substantially discharged; when the input voltage is valid and the capacitor is substantially discharged, setting the latch to a first state to begin recharging the capacitor; and responsive to the input voltage falling below the threshold voltage, setting the latch to a second state to being discharging the capacitor and setting the reset output signal to the invalid state, whereby setting the reset signal to the invalid state does not await discharging of the capacitor.

Claim 14

A method of generating a power-on reset signal in a CMOS integrated circuit responsive to a power supply input voltage comprising: providing first and second voltage comparators and a latch; in the first comparator, continuously comparing the power supply input voltage to a threshold voltage to form an indication that the input voltage is valid; in the second comparator, continuously monitoring a capacitor voltage to form an indication when the capacitor is substantially discharged; when the input voltage is valid and the capacitor is substantially discharged, setting the latch to a first state to begin recharging the capacitor; and responsive to the input voltage falling below the threshold voltage, setting the latch to a second state to being discharging the capacitor and setting the reset output signal to the invalid state, whereby setting the reset signal to the invalid state does not await discharging of the capacitor.