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US6044208A
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Incremental critical area computation for VLSI yield prediction
Assignee: GlobalFoundries Inc
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Filing: 1998-04-30
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Granted: 2000-03-28
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Expires: 2018-04-30
Abstract
Abstract An efficient method to compute critical area for shorts and breaks in rectilinear layouts in Very Large Scale Integrated (VLSI) circuits. The method is incremental and works in the L.sub.∞ geometry and has three major steps: Compute critical area for rectilinear layouts for both extra material and missing material defects (i.e., shorts and opens) by modeling defects as squares (which corresponds to the L.sub.∞ metric) instead of circles (Euclidean geometry). Treat the critical region for shorts and opens between any two edges or corners of the layout as a rectangle that grows uniformly as the defect radius increases. This is valid for rectilinear layouts and square defects (L.sub.∞ metric) . Use an incremental critical area algorithm for shorts and opens, which are computed for rectilinear layouts assuming square defects. Non-rectilinear layouts are approximated, first, by a rectilinear layout using a shape processing tool. The critical area for the rectilinear approximation is computed using the preferred incremental method.
Inventors
- 👤 Evanthia Papadopoulou
- 👤 Mark Alan Lavin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:12
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
108 words
A computer implemented method for critical area computation of defects in VLSI circuit manufacturing comprising the steps of: a) retrieving a design layer containing a plurality of design shapes; b) retrieving a list of defect sizes ordered in increasing size; c) determining seed critical regions for said design layer; d) listing said determined seed critical regions in an ordered list in order of increasing critical radius; e) identifying all seed critical regions having a critical radius less than a minimum defect size and removing each said identified seed critical region from said ordered list; and f) generating an actual critical region for each said identified seed critical region.
Claim 2
Dependent Claim
108 words
A computer implemented method for critical area computation of defects in VLSI circuit manufacturing comprising the steps of: a) retrieving a design layer containing a plurality of design shapes; b) retrieving a list of defect sizes ordered in increasing size; c) determining seed critical regions for said design layer; d) listing said determined seed critical regions in an ordered list in order of increasing critical radius; e) identifying all seed critical regions having a critical radius less than a minimum defect size and removing each said identified seed critical region from said ordered list; and f) generating an actual critical region for each said identified seed critical region.
Claim 3
Dependent Claim
47 words
The computer implemented method of claim 1 wherein the step (f) of generating an actual critical region comprises expanding each identified seed critical region by the difference between its critical radius and the critical radius of said minimum defect size, said generated actual critical region being rectangular.
Claim 4
Dependent Claim
106 words
The computer implemented method of claim 1 further comprising the steps of: g) identifying all seed critical regions having a critical radius less than a next smallest defect size and removing each said identified seed critical region from said ordered list, said next smallest defect size being identified as a current defect size; h) generating an actual critical region for each said identified seed critical region; i) generating additional critical region by expanding the critical region of the previous defect size by the difference between said current defect size and said previous defect size; and j) repeating steps (g) through (i) for all listed defect sizes.
Claim 5
Dependent Claim
25 words
The computer implemented method of claim 3 wherein the step (a) of retrieving a design layer further comprises unioning overlapping shapes in the design layer.
Claim 6
Dependent Claim
35 words
The computer implemented method of claim 4 wherein the step (b) of determining seed critical regions comprises the steps of: 1) determining all horizontal seed critical regions; and, 2) determining all vertical seed critical regions.
Claim 7
Dependent Claim
56 words
A method of integrated circuit chip design including checking the design according to the computer implemented method of claim 1 and further comprising the step of: g) modifying a design layer of said checked design based on said generated actual critical region to improve manufacturing yield; and h) rechecking said design using said computer implemented method.
Claim 8
Dependent Claim
25 words
A method of integrated circuit chip design according to claim 6 further comprising repeating steps (g) and (h) until a desired predicted yield is achieved.
Claim 9
Independent Claim
79 words
A system for analyzing defect critical areas of integrated circuit chips, said system comprising: means for storing a plurality of design shapes on a design layer; means for determining seed critical regions for said stored design shapes; means for organizing said determined seed critical regions according to a critical radius; means for selectively eliminating all seed critical regions less than a minimum defect size; and means for generating an actual critical region for each remaining said seed critical region.
Claim 10
Independent Claim
79 words
A system for analyzing defect critical areas of integrated circuit chips, said system comprising: means for storing a plurality of design shapes on a design layer; means for determining seed critical regions for said stored design shapes; means for organizing said determined seed critical regions according to a critical radius; means for selectively eliminating all seed critical regions less than a minimum defect size; and means for generating an actual critical region for each remaining said seed critical region.
Claim 11
Dependent Claim
47 words
A system for analyzing defect critical areas integrated circuit chips as in claim 8, further comprising means for expanding each identified seed critical region according to the difference between a critical radius of said identified seed critical region and the critical radius of said minimum defect size.
Claim 12
Dependent Claim
25 words
A system for analyzing defect critical areas integrated circuit chips as in claim 8, further comprising means for unioning overlapping shapes in the design layer.
References Cited (Backward Citations)
US3751647A
Cited
US5841893A
Cited
US5438527A
Cited
US5544256A
Cited
US5754432A
Cited
US5649169A
Cited
US5777901A
Cited
US5773315A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |