Parallel-pipelined image processing system

Claim 2

Apparatus for image processing a sequence of images representing a scene comprising: a cross-bar switch for selectively routing said sequence of images to a plurality of image storage elements, a pyramid processing circuit, and an arithmetic logic unit; a buffer, connected to an output port of the crossbar switch, for buffering images from the crossbar switch at video rates; a first digital signal processor and a second digital signal processor, connected to said buffer, for processing said images from said crossbar switch where said buffered images from said buffer are coupled directly to a random access memory of said first and second digital signal processors; and a global bus, connected to said crossbar switch and said first and second digital signal processors, for communicating information between said first digital signal processor, said second digital signal processor, said crossbar switch and an output connector.

Claim 3

The apparatus of claim 1 wherein said arithmetic logic unit transforms a two-dimensional image portion into a one-dimensional representation of the image portion.

Claim 4

The apparatus of claim 1 wherein said output connector is a VME P1 connector.

Claim 5

The apparatus of claim 1 further comprising a dynamic random access memory (DRAM), connected to said global bus, for storing information derived from processing said images.

Claim 6

The apparatus of claim 1 wherein said crossbar switch is an eight channel by ten bit switch that provides non-blocking interconnectivity of images.

Claim 7

The apparatus of claim 1 wherein the pyramid processing unit generates a Gaussian and Laplacian pyramid from images provided by the crossbar switch.

Claim 8

The apparatus of claim 1 wherein said image storage elements are video random access memories (VRAMs).

Claim 9

The apparatus of claim 1 further comprising a look up table connected to said arithmetic logic unit and said cross-bar switch.

Claim 10

The apparatus of claim 8 wherein said arithmetic logic unit further comprises means for pointwise subtracting landmark image patches in a reference image from corresponding image patches in a current image, and an illumination-compensated reference image from a current image.

Claim 11

The apparatus of claim 8 wherein said arithmetic logic unit further comprises means for performing image accumulation where pointwise image match measures are summed over an area.

Claim 12

The apparatus of claim 8 wherein said arithmetic logic unit further comprises means for performing row-wise masked image summation and energy computations, whereby a two-dimensional image area is reduced to a one-dimensional image.

Claim 13

The apparatus of claim 11 wherein said arithmetic logic unit further comprises means for generating image transpositions, where said row-wise masked image summation is performed column-wise.

Claim 14

The apparatus of claim 8 wherein said arithmetic logic unit further comprises: means for quantizing an image within said image sequence; and means for run-length encoding adjacent zeroes within a quantized image for performing video compression of said image within said sequence of images.

Claim 15

The apparatus of claim 1 further comprising an electrically erasable programmable read-only memory (EEPROM), connected to the global bus, for storing application programs.

Claim 16

The apparatus of claim 1 further comprising a static random access memory (SRAM) connected to said digital signal processor.

Claim 17

The apparatus of claim 1 further comprising a first static random access memory (SRAM) connected to said first digital signal processor and a second static random access memory (SRAM) connected to said second digital signal processor.

Claim 18

Apparatus for image processing comprising: an imaging sensor for generating a sequence of images representing a scene; a cross-bar switch for selectively routing said sequence of images to a plurality of image storage elements, a pyramid processing circuit, and an arithmetic logic unit, where said image storage elements are video random access memories (VRAMs), said pyramid processing circuit generates a Gaussian and Laplacian pyramid from images provided by the crossbar switch, and said arithmetic logic unit provides object detection functions; a first-in, first-out buffer, connected to an output port of the crossbar switch, for buffering images from the crossbar switch at video rates; a first digital signal processor, connected to said buffer, for processing said images from said crossbar switch; a second digital signal processor, connected to said buffer, for processing said images from said crossbar switch, where said buffered images from said first-in, first-out buffer are coupled directly to a random access memory of said second digital signal processor; a first static random access memory (SRAM) connected to said first digital signal processor, where said buffered images from said first-in, first-out buffer are coupled directly to said first SRAM; a second static random access memory (SRAM) connected to said second digital signal processor, where said buffered images from said first-in, first-out buffer are coupled directly to said second SRAM; a global bus, connected to said crossbar switch and said digital signal processor, for communicating between said digital signal processor, said crossbar switch and an output connector; a dynamic random access memory (DRAM), connected to said global bus, for storing information derived from processing said images by said first and second digital signal processors; and a EEPROM, connected to the global bus, for storing application programs to be executed by said arithmetic logic unit and said digital signal processors.

Claim 19

Apparatus for image processing comprising: an imaging sensor for generating a sequence of images representing a scene; a cross-bar switch for selectively routing said sequence of images to a plurality of image storage elements, a pyramid processing circuit, and an arithmetic logic unit, where said image storage elements are video random access memories (VRAMs), said pyramid processing circuit generates a Gaussian and Laplacian pyramid from images provided by the crossbar switch, and said arithmetic logic unit provides object detection functions; a first-in, first-out buffer, connected to an output port of the crossbar switch, for buffering images from the crossbar switch at video rates; a first digital signal processor, connected to said buffer, for processing said images from said crossbar switch; a second digital signal processor, connected to said buffer, for processing said images from said crossbar switch, where said buffered images from said first-in, first-out buffer are coupled directly to a random access memory of said second digital signal processor; a first static random access memory (SRAM) connected to said first digital signal processor, where said buffered images from said first-in, first-out buffer are coupled directly to said first SRAM; a second static random access memory (SRAM) connected to said second digital signal processor, where said buffered images from said first-in, first-out buffer are coupled directly to said second SRAM; a global bus, connected to said crossbar switch and said digital signal processor, for communicating between said digital signal processor, said crossbar switch and an output connector; a dynamic random access memory (DRAM), connected to said global bus, for storing information derived from processing said images by said first and second digital signal processors; and a EEPROM, connected to the global bus, for storing application programs to be executed by said arithmetic logic unit and said digital signal processors.

Claim 20

The apparatus of claim 17 further comprising a look up table connected to said arithmetic logic unit and said cross-bar switch.

Claim 21

The apparatus of claim 17 wherein said arithmetic logic unit further comprises means for pointwise subtracting landmark image patches in a reference image from corresponding image patches in a current image, and an illumination-compensated reference image from a current image.

Claim 22

The apparatus of claim 17 wherein said arithmetic logic unit further comprises means for performing image accumulation where pointwise image match measures are summed over an area.

Claim 23

The apparatus of claim 17 wherein said arithmetic logic unit further comprises means for performing row-wise masked image summation and energy computations, whereby a two-dimensional image area is reduced to a one-dimensional image.

Claim 24

The apparatus of claim 21 wherein said arithmetic logic unit further comprises means for generating image transpositions, where said row-wise masked image summation is performed column-wise.

Claim 25

The apparatus of claim 17 wherein said arithmetic logic unit further comprises: means for quantizing an image within said image sequence; and means for run-length encoding adjacent zeroes within a quantized image for performing video compression of said image within said sequence of images.

Claim 26

A traffic monitoring system for processing a sequence of images representing a scene of traffic comprising: a cross-bar switch for selectively routing said sequence of images to a plurality of image storage elements, a pyramid processing circuit, and an arithmetic logic unit, where said pyramid processing circuit and said arithmetic logic unit process the sequence of images to generate a reference image representing stationary objects within the scene and generate motion images representing objects that are moving relative to the reference image; a buffer, connected to an output port of the crossbar switch, for buffering the reference image and the motion images from the crossbar switch at video rates; a digital signal processor, connected to said buffer, for processing said motion images and said reference image from said crossbar switch, where the buffered images from said buffer are coupled directly to a random access memory of said digital signal processor and said digital signal processor identifies the moving objects; and a global bus, connected to said crossbar switch and said digital signal processor, for communicating information between said digital signal processor, said crossbar switch and an output connector.

Claim 27

A traffic monitoring system for processing a sequence of images representing a scene of traffic comprising: a cross-bar switch for selectively routing said sequence of images to a plurality of image storage elements, a pyramid processing circuit, and an arithmetic logic unit, where said pyramid processing circuit and said arithmetic logic unit process the sequence of images to generate a reference image representing stationary objects within the scene and generate motion images representing objects that are moving relative to the reference image; a buffer, connected to an output port of the crossbar switch, for buffering the reference image and the motion images from the crossbar switch at video rates; a digital signal processor, connected to said buffer, for processing said motion images and said reference image from said crossbar switch, where the buffered images from said buffer are coupled directly to a random access memory of said digital signal processor and said digital signal processor identifies the moving objects; and a global bus, connected to said crossbar switch and said digital signal processor, for communicating information between said digital signal processor, said crossbar switch and an output connector.

Claim 28

The traffic monitoring system of claim 24 wherein said arithmetic logic unit and digital signal processor further comprises means for updating said reference image with information within said images, where said information used for updating the reference image only represents stationary objects within the scene and substantially disregards moving objects and temporarily stationary objects within the scene.

Claim 29

The traffic monitoring system of claim 24 wherein said arithmetic logic unit and digital signal processor further comprises means for modifying said reference image using image information within said images regarding changes to illumination of the scene.