Pyramid processor integrated circuit

Claim 1

A pyramid processor comprising: means for receiving a first and a second digital data input signal, each including a data signal component and a timing signal component; first means, responsive to a first control signal, for selectively combining the respective data signal components of the first and second digital data signals to generate a third digital data signal, and for delaying and selectively combining the respective timing signal components of the first and second digital data signals to compensate for delays incurred in processing the first and second data signals and for combining the compensated timing signal with the third digital data signal; two-dimensional digital filter means, including first and second component filters, each of said component filters having a respective tapped delay line, for processing the data signal component of the third digital data signal in accordance with a programmed transfer function to produce a first filtered signal; means, coupled to the two-dimensional filter for delaying the timing signal component of the third digital data signal to compensate for processing delays incurred by the filtering of the third digital data signal; means coupled to the filter means to receive the filtered signal and an unfiltered signal provided by the tapped delay line of the first component filter and responsive to a second control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal; and control means, responsive to a programming signal to generate the first and second control signals.