US6044005A
Expired / Lapsed
US
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Content addressable memory storage device
Assignee: FOOTHILLS IP LLC
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Filing: 1999-02-03
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Granted: 2000-03-28
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Expires: 2019-02-03
Abstract
Abstract Binary and ternary content addressable memory (CAM) cells are disclosed, which permit the construction of high-performance, large-capacity CAM arrays. The CAM cells have a reduced match line power dissipation, and a reduced compare line loading that is data independent, and full swing comparator output. Match line power dissipation is limited by means of a NAND chain match line. Loading on compare lines is limited by connecting compare lines to the gate terminals of the CAM cell comparator. Local precharge devices at the output of the comparator provide full swing compare logic levels for faster matching. The same precharge devices also serve as an active reset for the comparator. Comparator circuits for ternary CAM cells further employ disable means, which makes the comparison operation conditional on the value stored in the mask memory element. The use of disable means allows the mask and data to be stored separately in a non-encoded form. As a result, mask and data information may be read and written independently of one another.
Inventors
- 👤 Garnet Fredrick Randall Gibson
- 👤 Farhard Shafai
- 👤 Jason Edward Podaima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:54
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C15/046
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
131 words
A content addressable memory cell comprising: a memory element for storing a data bit, said memory element having a cell node; access means coupled to said memory element and to a bit line, wherein said access means is responsive to a word line for coupling said cell node to said bit line during a change in signal level in said word line in a first predetermined direction; comparator means coupled to said cell node and to a compare line for performing a comparison between signal levels at said cell node and said compare line, during a change in signal level in said compare line in a second predetermined direction, and for providing a comparator output indicative of said comparison; and resetting means for resetting said comparator means subsequent to said comparison.
Claim 2
Dependent Claim
131 words
A content addressable memory cell comprising: a memory element for storing a data bit, said memory element having a cell node; access means coupled to said memory element and to a bit line, wherein said access means is responsive to a word line for coupling said cell node to said bit line during a change in signal level in said word line in a first predetermined direction; comparator means coupled to said cell node and to a compare line for performing a comparison between signal levels at said cell node and said compare line, during a change in signal level in said compare line in a second predetermined direction, and for providing a comparator output indicative of said comparison; and resetting means for resetting said comparator means subsequent to said comparison.
Claim 3
Dependent Claim
56 words
A content addressable memory cell as defined in claim 1, further comprising match means responsive to the comparator output, wherein said content addressable memory cell is a member of a plurality of similarly formed content addressable memory cells accessing a match line driven by respective said match means of each of the content addressable memory cells.
Claim 4
Dependent Claim
46 words
A content addressable memory cell as defined in claim 2, wherein the match means for each one of the plurality of similar content addressable memory cells comprises one of a corresponding plurality of logic NAND devices positioned in series with one another along the match line.
Claim 5
Dependent Claim
51 words
A content addressable memory cell as defined in claim 2, wherein the match means for each one of the plurality of similar content addressable memory cells comprises one of a corresponding plurality of logic NOR devices positioned in parallel with one another between a power supply node and the match line.
Claim 6
Dependent Claim
19 words
A content addressable memory cell as defined in claim 1, wherein the memory element comprises a static memory device.
Claim 7
Dependent Claim
19 words
A content addressable memory cell as defined in claim 1, wherein the memory element comprises a non-volatile memory device.
Claim 8
Dependent Claim
19 words
A content addressable memory cell as defined in claim 1, wherein the memory element comprises a single-ended memory device.
Claim 9
Dependent Claim
19 words
A content addressable memory cell as defined in claim 1, wherein the memory element comprises a dynamic memory device.
Claim 10
Dependent Claim
31 words
A content addressable memory cell as defined in claim 1, wherein the access means comprises transistor means responsive to the word line for coupling the cell node to the bit line.
Claim 11
Dependent Claim
31 words
A content addressable memory cell as defined in claim 1, wherein the comparator means comprises transistor means responsive to the compare line for coupling the cell node to the comparator output.
Claim 12
Dependent Claim
61 words
A content addressable memory cell as defined in claim 1, wherein the comparator means comprises a pair of a first and a second transistor means in a series configuration for coupling the cell node to a power supply node, wherein said first transistor means is responsive to the compare line and said second transistor means is responsive to the cell node.
Claim 13
Dependent Claim
32 words
A content addressable memory cell as defined in claim 1, wherein the resetting means comprises transistor means responsive to the compare line for coupling the comparator output to a power supply node.
Claim 14
Dependent Claim
32 words
A content addressable memory cell as defined in claim 1, wherein the resetting means comprises transistor means responsive to a precharge line for coupling the comparator output to a power supply node.
Claim 15
Dependent Claim
83 words
A content addressable memory cell as defined in claim 1, further comprising: a mask memory element for storing a mask bit, said mask memory element having a mask cell node; and mask access means coupled to said mask memory element and to a mask bit line; wherein said mask access means is responsive to the word line for coupling said mask cell node to said mask bit line during a change in signal level in said word line in the first predetermined direction.
Claim 16
Dependent Claim
197 words
A content addressable memory cell comprising: a) a data memory element for storing a data bit, said data memory element having a data cell node; a mask memory element for storing a mask bit, said mask memory element having a mask cell node; data access means coupled to said data memory element and to a data bit line, mask access means coupled to said mask memory element and to a mask bit line; wherein said data and mask access means are responsive to a word line for coupling said data and mask cell nodes to said data and mask bit lines respectively during a change in signal level in said word line in a first predetermined direction; comparator means coupled to said data and mask cell nodes and to a compare line for performing a comparison between signal levels at said data cell node and said compare line, during a change in signal level in said compare line in a second predetermined direction, and for providing a comparator output indicative of said comparison; and disable means responsive to said mask cell node for disabling said comparator output when the mask cell node has a predetermined signal level.
Claim 17
Dependent Claim
197 words
A content addressable memory cell comprising: a) a data memory element for storing a data bit, said data memory element having a data cell node; a mask memory element for storing a mask bit, said mask memory element having a mask cell node; data access means coupled to said data memory element and to a data bit line, mask access means coupled to said mask memory element and to a mask bit line; wherein said data and mask access means are responsive to a word line for coupling said data and mask cell nodes to said data and mask bit lines respectively during a change in signal level in said word line in a first predetermined direction; comparator means coupled to said data and mask cell nodes and to a compare line for performing a comparison between signal levels at said data cell node and said compare line, during a change in signal level in said compare line in a second predetermined direction, and for providing a comparator output indicative of said comparison; and disable means responsive to said mask cell node for disabling said comparator output when the mask cell node has a predetermined signal level.
Claim 18
Dependent Claim
56 words
A content addressable memory cell as defined in claim 15, further comprising match means responsive to the comparator output, wherein said content addressable memory cell is a member of a plurality of similarly formed content addressable memory cells accessing a match line driven by respective said match means of each of the content addressable memory cells.
Claim 19
Dependent Claim
51 words
A content addressable memory cell as defined in claim 16, wherein the match means for each one of the plurality of similar content addressable memory cells comprises one of a corresponding plurality of logic NOR devices positioned in parallel with one another between a power supply node and the match line.
Claim 20
Dependent Claim
46 words
A content addressable memory cell as defined in claim 16, wherein the match means for each one of the plurality of similar content addressable memory cells comprises one of a corresponding plurality of logic NAND devices positioned in series with one another along the match line.
Claim 21
Dependent Claim
23 words
A content addressable memory cell as defined in claim 18, wherein the disable means comprises transistor means for shunting the logic NAND device.
Claim 22
Dependent Claim
23 words
A content addressable memory cell as defined in claim 15, further comprising resetting means for resetting said comparator means subsequent to said comparison.
Claim 23
Dependent Claim
32 words
A content addressable memory cell as defined in claim 20, wherein the resetting means comprises transistor means responsive to the compare line for coupling the comparator output to a power supply node.
Claim 24
Dependent Claim
32 words
A content addressable memory cell as defined in claim 20, wherein the resetting means comprises transistor means responsive to a precharge line for coupling the comparator output to a power supply node.
Claim 25
Dependent Claim
26 words
A content addressable memory cell as defined in claim 15, wherein the disable means comprises transistor means for decoupling the comparator output from the comparator means.
Claim 26
Dependent Claim
27 words
A content addressable memory cell as defined in claim 15, wherein the disable means comprises transistor means for decoupling the data cell node from the comparator means.
Claim 27
Dependent Claim
22 words
A content addressable memory cell as defined in claim 15, wherein the disable means comprises transistor means for shunting the comparator means.
Claim 28
Dependent Claim
27 words
A content addressable memory cell as defined in claim 15, wherein each of the data memory element and the mask memory element comprises a static memory device.
Claim 29
Dependent Claim
27 words
A content addressable memory cell as defined in claim 15, wherein each of the data memory element and the mask memory element comprises a non-volatile memory device.
Claim 30
Dependent Claim
27 words
A content addressable memory cell as defined in claim 15, wherein each of the data memory element and the mask memory element comprises a single-ended memory device.
Claim 31
Dependent Claim
27 words
A content addressable memory cell as defined in claim 15, wherein each of the data memory element and the mask memory element comprises a dynamic memory device.
Claim 32
Dependent Claim
58 words
A content addressable memory cell as defined in claim 15, wherein the data access means comprises transistor means responsive to the word line for coupling the data cell node to the data bit line, and the mask access means comprises transistor means responsive to the word line for coupling the mask cell node to the mask bit line.
Claim 33
Dependent Claim
32 words
A content addressable memory cell as defined in claim 15, wherein the comparator means comprises transistor means responsive to the compare line for coupling the data cell node to the comparator output.
Claim 34
Dependent Claim
62 words
A content addressable memory cell as defined in claim 15, wherein the comparator means comprises a pair of a first and a second transistor means in a series configuration for coupling the data cell node to a power supply node, said first transistor means being responsive to the compare line and said second transistor means being responsive to the data cell node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |