US5568415A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Content addressable memory having a pair of memory cells storing don't care states for address translation
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-02-19
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Granted: 1996-10-22
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Expires: 2013-02-19
Abstract
Abstract A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors connects a common node to a respective one of a pair of address lines, and another of the transistors connects the common node to a potential of a predefined logic level. Each of the transistors has a gate receiving a logic level of the bit of information stored in a respective memory cell so that one of the transistors is conductive in response to the logic level of the bit of the information when the other of the transistors is not conductive in response to the logic level of the bit of information. Each of the memory cells also includes a transistor connected to the match line and having a gate connected to the common node. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care states permit multiple virtual page numbers to match a single entry storing information for multiple physical pages. The invalid state eliminates the need for a dedicated valid bit in each entry.
Inventors
- 👤 Edward J. McLellan
- 👤 Bruce A. Gieseke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:53
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G11; G11C; G11C15/00; G11C15/04; G06F2212/00; G06F2212/65; G06F2212/652
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
215 words
A content addressable memory for storing information including a "don't care" state, comparing the stored information to address signals asserted on a pair of address lines, and asserting a match signal on a match line when the stored information matches address information asserted on said address lines, said content addressable memory comprising: a pair of memory cells, each of said memory cells storing a respective bit of said stored information, each of said memory cells including a pair of transistors, one of said transistors connecting a common node to a respective one of said address lines, another of said transistors connecting said common node to a potential of a predefined logic level, each of said transistors having a gate receiving a logic level or inverted logic level of the bit of information stored in a respective one of said memory cells so that one of said transistors is conductive in response to the logic level of the bit of information stored in the respective one of said memory cells when the other of said transistors is not conductive in response to the logic level of the bit of information stored in the respective one of said memory cells; and a transistor connected to said match line and having a gate connected to said common node.
Claim 2
Dependent Claim
215 words
A content addressable memory for storing information including a "don't care" state, comparing the stored information to address signals asserted on a pair of address lines, and asserting a match signal on a match line when the stored information matches address information asserted on said address lines, said content addressable memory comprising: a pair of memory cells, each of said memory cells storing a respective bit of said stored information, each of said memory cells including a pair of transistors, one of said transistors connecting a common node to a respective one of said address lines, another of said transistors connecting said common node to a potential of a predefined logic level, each of said transistors having a gate receiving a logic level or inverted logic level of the bit of information stored in a respective one of said memory cells so that one of said transistors is conductive in response to the logic level of the bit of information stored in the respective one of said memory cells when the other of said transistors is not conductive in response to the logic level of the bit of information stored in the respective one of said memory cells; and a transistor connected to said match line and having a gate connected to said common node.
Claim 3
Dependent Claim
30 words
The content addressable memory as claimed in claim 1, wherein said potential of a predefined logic level is ground potential of a semiconductor substrate including semiconductor material of said transistors.
Claim 4
Dependent Claim
29 words
The content addressable memory as claimed in claim 1, further comprising an address bit generator connected to said address lines to assert complementary address signals on said address lines.
Claim 5
Dependent Claim
90 words
The content addressable memory as claimed in claim 1, wherein each of said memory cells includes a pair of cross-coupled inverters for storing a respective bit of said stored information, one of said inverters having an output connected to the gate of said one of said pair of transistors, and the other of said pair of inverters having an output connected to the gate of said other of said pair of transistors, so that complementary logic levels are asserted on the gates of the transistors of said pair of transistors.
Claim 6
Dependent Claim
62 words
The content addressable memory as claimed in claim 1, wherein each of said memory cells further comprises a transistor having a gate connected to a flush line for setting, in response to a flush signal on said flush line, the bit of information stored in a respective memory cell to a logic state rendering said one of said pair of transistors non-conductive.
Claim 7
Dependent Claim
86 words
The content addressable memory as claimed in claim 5, further comprising a write line and pair of data input lines, and wherein each of said memory cells further comprises a transistor connected to a respective one of said data input lines and having a gate connected to said write line for setting a respective bit of information to a logic state specified by a data signal asserted on said respective one said data input lines when a write enable signal is asserted on said write line.
Claim 8
Dependent Claim
107 words
The content addressable memory as claimed in claim 6, further comprising a logic circuit connecting said pair of data input lines to a single data line of a data bus and to a mask bit line so that when a mask bit is asserted on said mask bit line and a write enable signal is asserted on said write line, data are written into said pair of memory cells representing said "don't care" state, and when a mask bit is not asserted on said mask bit line and a write enable signal is asserted on said write line, data are written into said pair of memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |