Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed

Claim 3

The method according to claim 1 wherein said granularity hint is two bits of each one of said page table entries, providing four possible values of said granularity hint.

Claim 4

The method according to claim 1 wherein said page frame number addresses a page of 8Kbyte-to-64Kbyte in size.

Claim 5

The method according to claim 1 wherein said granularity hint is two bits of each one of said page table entries, providing an indication of four different numbers of pages to be referenced by each one of said page table entries.

Claim 6

The method according to claim 4 wherein said four different numbers of pages to be referenced by each one of said page table entries are 1, 8, 64 and 512 pages.

Claim 9

The method according to claim 6 wherein said granularity hint is two bits of each one of said page table entries providing four possible values of said granularity hint.

Claim 10

The method according to claim 6 wherein said page frame number addresses a page of 8Kbyte-to-64Kbyte in size.

Claim 11

The method according to claim 8 wherein said granularity hint is two bits of each one of said page table entries, providing an indication of four different numbers of pages to be referenced by said page table entry.

Claim 12

The method according to claim 9 wherein said four different numbers of pages to be referenced by each one of said page table entries are 1, 8, 64 and 512 pages.

Claim 13

A processor comprising: a) accessing means for fetching instructions from an external memory, decoding means coupled to said accessing means for decoding said instructions, and execution means coupled to said decoding means for executing said instructions, said accessing means including means for accessing said external memory for read and write data for said execution means; b) the accessing means including address generator means for generating a virtual address used for said fetching of instructions and used for said accessing said external memory for data; c) translating means included in said accessing means for translating said virtual address to a physical address for said external memory, said translating means including a translation buffer storing selected page table entries, each one of said selected page table entries including a page frame number referencing a page of said external memory and each one of said selected page table entries including a granularity hint, said granularity hint having one or more bits indicating a number of pages to be accessed in said external memory using the page frame number from said translation buffer and using a first part of said virtual address; d) said translating means generating a physical address for said external memory using the page frame number from said translation buffer and using a second part of said virtual address.

Claim 14

A processor comprising: a) accessing means for fetching instructions from an external memory, decoding means coupled to said accessing means for decoding said instructions, and execution means coupled to said decoding means for executing said instructions, said accessing means including means for accessing said external memory for read and write data for said execution means; b) the accessing means including address generator means for generating a virtual address used for said fetching of instructions and used for said accessing said external memory for data; c) translating means included in said accessing means for translating said virtual address to a physical address for said external memory, said translating means including a translation buffer storing selected page table entries, each one of said selected page table entries including a page frame number referencing a page of said external memory and each one of said selected page table entries including a granularity hint, said granularity hint having one or more bits indicating a number of pages to be accessed in said external memory using the page frame number from said translation buffer and using a first part of said virtual address; d) said translating means generating a physical address for said external memory using the page frame number from said translation buffer and using a second part of said virtual address.

Claim 15

The processor according to claim 11 in combination with a memory apparatus external to said processor, said memory apparatus including said external memory storing a page table of said page table entries.

Claim 16

The processor according to claim 11 wherein said second part of said virtual address is dependent upon a content of said one or more bits of said granularity hint.

Claim 17

The processor according to claim 12 wherein each one of said selected page table entries also contains predetermined bits defining protection and access rights information, for said page of said external memory, and wherein all of the number of pages indicated by said granularity hint must have the said predetermined bits defining protection and access rights information.

Claim 18

A processor system having a CPU and a memory, the processor system comprising: a) fetching and execution means is the CPU for fetching instructions from said memory, decoding said instructions, and executing said instructions, said executing including accessing said memory for read and write data; b) said fetching and execution means in said CPU including means for generating virtual addresses used by said CPU for said fetching of instructions and said accessing said memory for data; c) a page table stored in said memory, said page table containing a plurality of page table entries, each one of said page table entries including a page frame number referencing a page of said memory and a granularity hint, said granularity hint having one or more bits indicating a number of pages of said memory following said selected page to be referenced by said page frame number; d) said fetching and execution means in said CPU including means for translating said virtual addresses to physical addresses for sending to said memory, the means for translating including a translation buffer storing page table entries of recently used address translations; e) and means for addressing said memory using the page frame number from said translation buffer and using a part of each of said virtual addresses.

Claim 19

A processor system having a CPU and a memory, the processor system comprising: a) fetching and execution means is the CPU for fetching instructions from said memory, decoding said instructions, and executing said instructions, said executing including accessing said memory for read and write data; b) said fetching and execution means in said CPU including means for generating virtual addresses used by said CPU for said fetching of instructions and said accessing said memory for data; c) a page table stored in said memory, said page table containing a plurality of page table entries, each one of said page table entries including a page frame number referencing a page of said memory and a granularity hint, said granularity hint having one or more bits indicating a number of pages of said memory following said selected page to be referenced by said page frame number; d) said fetching and execution means in said CPU including means for translating said virtual addresses to physical addresses for sending to said memory, the means for translating including a translation buffer storing page table entries of recently used address translations; e) and means for addressing said memory using the page frame number from said translation buffer and using a part of each of said virtual addresses.

Claim 20

The processor system according to claim 15 wherein said part of said virtual address contains a number of bits dependent upon a content of said one or more bits of said granularity hint.

Claim 21

The processor system according to claim 15 wherein said granularity hint in each one of said page table entries is used by said means for addressing to define the number of pages referenced by said page frame number only if page table entries for all of said number of pages contain a predetermined content of protection bits.

Claim 22

The processor system according to claim 15 wherein said instructions fetched from said memory are all of a fixed length.

Claim 23

The processor system according to claim 15 wherein each one of said page table entries also contains a plurality of bits of protection and access rights information, and wherein all of said plurality of bits in said page table entries for all of the number of pages indicated by said granularity hint are the same.

Claim 24

The processor system according to claim 15 wherein said one or more bits of said granularity hint in each one of said page table entries is two bits, and said two bits provide four possible values of said granularity hint.

Claim 25

The method according to claim 5 wherein each one of said page table entries includes a number of bits of protection information, and each one of said number of pages defined by said granularity hint has the same value for all bits of said number of bits of page protection information.

Claim 26

The method according to claim 10 wherein each one of said page table entries includes a number of bits of protection information, and each one of said number of pages defined by said granularity hint has the same value for all bits of said number of bits of page protection information.