US3800291A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system memory relocation apparatus and method
Assignee: International Business Machines Corp
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Filing: 1972-09-21
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Granted: 1974-03-26
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Expires: 1992-09-21
Abstract
Abstract A data processing system having a virtual memory comprising pages which are relocatable between various levels of physical storage. The virtual memory primarily contains information comprising instructions arranged sequentially so that once a virtual address has been translated to the physical address in high speed memory, the physical address can be incremented to fetch the next sequential information. Branch instructions may branch to the address of information on the same or another page. The branch instruction includes an indicator as to whether the branch address is a physical address on the same or another page or a virtual address on another page. Only when a virtual address is encountered is the relocation table employed to convert the virtual address to a physical address and to load the page if necessary.
Inventors
- 👤 J Cocke
- 👤 D Helman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:20
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06F2212/00; G06F2212/65; G06F2212/655
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
177 words
In a data processing apparatus including memory addressing means, memory means having both physical and virtual addressing locations for storing instructions and supplying addressed instructions at an output thereof in response to said memory addressing means, and branch condition test means for executing a branch instruction appearing at said memory output to determine whether the branch condition has been met and to supply a signal upon said condition having been met, the improvement thereto comprising: said branch instruction including a branch address and an indicator as to whether said branch address is physical or virtual; incrementing means responsive to each instruction supplied at said memory output not causing said branch condition test means to generate said signal, for incrementing the currEnt physical address in said memory addressing means by a predetermined amount; first means responsive to said signal and the physical indication by said indicator for supplying said branch address to said memory addressing means; and second means responsive to said signal and the virtual indication by said indicator for signalling that said branch address requires translation.
Claim 2
Dependent Claim
177 words
In a data processing apparatus including memory addressing means, memory means having both physical and virtual addressing locations for storing instructions and supplying addressed instructions at an output thereof in response to said memory addressing means, and branch condition test means for executing a branch instruction appearing at said memory output to determine whether the branch condition has been met and to supply a signal upon said condition having been met, the improvement thereto comprising: said branch instruction including a branch address and an indicator as to whether said branch address is physical or virtual; incrementing means responsive to each instruction supplied at said memory output not causing said branch condition test means to generate said signal, for incrementing the currEnt physical address in said memory addressing means by a predetermined amount; first means responsive to said signal and the physical indication by said indicator for supplying said branch address to said memory addressing means; and second means responsive to said signal and the virtual indication by said indicator for signalling that said branch address requires translation.
Claim 3
Dependent Claim
73 words
The apparatus of Claim 1 wherein: said branch condition test means additionally is arranged to supply a second signal upon said condition not having been met; and said incrementing means is responsive to each non-branch instruction supplied at said memory output and is responsive to said second signal for incrementing the last address of said memory addressing means by a predetermined amount and supplying said incremented physical address to said memory addressing means.
Claim 4
Dependent Claim
101 words
The apparatus of Claim 1 wherein: said branch address includes a page portion and an offset portion; offset means is responsive to said signal from said branch condition test means to supply said offset portion of said branch address to said memory address means; said first means is responsive to said signal and the physical indication by said indicator for supplying said page portion of said branch address to said memory address means; and said second means is responsive to said signal and the virtual indication by said indicator for signalling that the page portion of said branch address requires translation.
Claim 5
Dependent Claim
20 words
The apparatus of Claim 3 wherein: said incrementing means, said offset means and said first means each includes gating means.
Claim 6
Dependent Claim
175 words
Data processing memory relocation apparatus comprising: memory addressing means for providing addressing signals; instruction memory means having both physical and virtual addressing locations for storing instructions, including branch instructions having a branch address and an indicator whether said branch address is physical or virtual, and supplying addressed instructions at an output thereof in response to said addressing signal; branch condition test means for testing a branch instruction appearing at said memory output to determine whether the branch condition has been met and to supply a signal upon said condition having been met; incrementing means responsive to each instruction portion of said memory output that does not cause said branch condition test means to generate said signal, for incrementing the current physical address in said memory addressing means by an address; and first means responsive to said signal and the physical indication by said indicator for supplying said branch address to said memory addressing means; and second means responsive to said signal and the virtual indication by said indicator for providing an address translation request signal.
Claim 7
Dependent Claim
175 words
Data processing memory relocation apparatus comprising: memory addressing means for providing addressing signals; instruction memory means having both physical and virtual addressing locations for storing instructions, including branch instructions having a branch address and an indicator whether said branch address is physical or virtual, and supplying addressed instructions at an output thereof in response to said addressing signal; branch condition test means for testing a branch instruction appearing at said memory output to determine whether the branch condition has been met and to supply a signal upon said condition having been met; incrementing means responsive to each instruction portion of said memory output that does not cause said branch condition test means to generate said signal, for incrementing the current physical address in said memory addressing means by an address; and first means responsive to said signal and the physical indication by said indicator for supplying said branch address to said memory addressing means; and second means responsive to said signal and the virtual indication by said indicator for providing an address translation request signal.
Claim 8
Dependent Claim
73 words
The apparatus of Claim 5 wherein: said branch condition test means additionally is arranged to supply a second signal upon said condition not having been met; and said incrementing means is responsive to each non-branch instruction supplied at said memory output and is responsive to said second signal for incrementing the last address of said memory addressing means by a predetermined amount and supplying said incremented physical address to said memory addressing means.
Claim 9
Dependent Claim
111 words
The apparatus of Claim 5 wherein: each said branch address stored by said instruction memory means includes a page portion and an offset portion; offset means is provided which is responsive to said signal from said branch condition test means to supply said offset portion of said branch address to said memory address means; said first means is responsive to said signal and the physical indication by said indicator for supplying said page portion of said branch address to said memory address means; and said second means is responsive to said signal and the virtual indication by said indicator for signalling that the page poRtion of said branch address requires translation.
Claim 10
Dependent Claim
23 words
The apparatus of Claim 3 wherein: said incrementing means, said offset means, said first means and said second means each includes gating means.
Claim 11
Independent Claim
201 words
A method for operating a data processing apparatus in response to instructions, including branch instructions having a branch address and an indicator whether said branch address is physical or virtual, said data processing apparatus including memory addressing means, memory means having both physical and virtual addressing locations for storing instructions and supplying instructions addressed by said memory addressing means, and branch condition test means for executing branch instructions supplied thereto, comprising the steps of: responding to said instructions supplied at the output of said memory means to determine whether said instruction is a branch instruction; testing a branch instruction when one occurs to determine whether the branch condition has been met; incrementing the current physical address when said instruction is other than a branch instruction or if it is a branch instruction and the testing of said branch instruction determines said branch condition has not been met; testing said indicator when testing of a branch instruction determines a branch condition has been met; supplying the branch address to said memory address means when in response to a physical indication from said tested indicator; and signaling for translation of said branch address in response to a virtual indication from said tested indicator.
Claim 12
Independent Claim
201 words
A method for operating a data processing apparatus in response to instructions, including branch instructions having a branch address and an indicator whether said branch address is physical or virtual, said data processing apparatus including memory addressing means, memory means having both physical and virtual addressing locations for storing instructions and supplying instructions addressed by said memory addressing means, and branch condition test means for executing branch instructions supplied thereto, comprising the steps of: responding to said instructions supplied at the output of said memory means to determine whether said instruction is a branch instruction; testing a branch instruction when one occurs to determine whether the branch condition has been met; incrementing the current physical address when said instruction is other than a branch instruction or if it is a branch instruction and the testing of said branch instruction determines said branch condition has not been met; testing said indicator when testing of a branch instruction determines a branch condition has been met; supplying the branch address to said memory address means when in response to a physical indication from said tested indicator; and signaling for translation of said branch address in response to a virtual indication from said tested indicator.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-25 | 1977-09-24 | 1978-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-25 | 1981-09-24 | 1982-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-25 | 1985-09-24 | 1986-03-26 | $7700.00 | Window Closed / Lapsed |