Nonvolatile content addressable memory

Claim 2

A multiple-valued NVCAM comprising: a j row by k column memory cell array, the cells of each column being connected to m bit lines, each cell including m switching means and m ferroelectric capacitors, each of the ferroelectric capacitors in one cell having a different capacitance, j, k and m being integers, one switching means and the respective ferroelectric capacitor being connected in series between the respective bit line and a drive line, the switching means being asserted by a signal on a respective word line; and data sensing means for comparing the data stored in the cells to reference data, the data sensing means comprising: data acquisition means for acquiring the comparison results; and j data comparison means, each data comparison means being connected to the cells of the respective column and the data acquire means, each data comparison means comparing the data stored in the cells of the respective column to the reference data to provide comparison results to the data acquire means.

Claim 3

The multiple-valued NVCAM of claim 1, wherein the m ferroelectric capacitors of one cell are charged by different voltages of "1" data on the respective bit line.

Claim 4

The multiple-valued NVCAM of claim 1, wherein each of the ferroelectric capacitors has a different size in area.

Claim 5

A multiple-valued NVCAM comprising: a j row by k column memory cell array, the cells of each column being connected to m bit lines, each cell including m switching means and m ferroelectric capacitors, j, k and m being integers, one switching means and the respective ferroelectric capacitor being connected in series between the respective bit line and a drive line, the switching means being asserted by a signal on a respective word line; and data sensing means for comparing the data stored in the cells to reference data, m being two, the bit lines of each column being first and second bit lines, the cell including first and second ferroelectric capacitors, and the NVCAM stores four-valued data, the capacitor area size of the first ferroelectric capacitor being different from that of the second ferroelectric capacitor.

Claim 6

A multiple-valued NVCAM comprising: a j row by k column memory cell array, the cells of each column being connected to m bit lines, each cell including m switching means and m ferroelectric capacitors, j, k and m being integers, one switching means and the respective ferroelectric capacitor being connected in series between the respective bit line and a drive line, the switching means being asserted by a signal on a respective word line; and data sensing means for comparing the data stored in the cells to reference data, m being two, the bit lines of each column being first and second bit lines, the cell including first and second ferroelectric capacitors, and the NVCAM stores four-valued data, the capacitor area size of the first ferroelectric capacitor being different from that of the second ferroelectric capacitor.

Claim 7

The multiple-valued NVCAM of claim 4, wherein each cell including first and second switching means and first and second ferroelectric capacitors, the first switching means and the first ferroelectric capacitor being connected in series between the first bit line and the drive line, the second switching means and the second ferroelectric capacitor being connected in series between the second bit line and the drive line, the first and second switching means being asserted by the respective word line.

Claim 8

The multiple-valued NVCAM of claim 4, wherein the data comparison means comprising: j pairs of third and fourth switching means connected in series between the first and the second bit lines of the respective column, the third and fourth switching means being asserted by a control line; j data store means between the junction of the third and fourth switching means of the respective column and a data line, the data line being for receiving reference data; j matching means connected to the junction of the third and fourth switching means of the respective column and the data acquire means; and j pairs of fifth and sixth switching means connected between the respective bit lines and the data acquire means, the fifth and sixth switching means being asserted by a sense line.

Claim 9

The multiple-valued NVCAM of claim 5, wherein the data store means includes a capacitor.

Claim 10

The multiple-valued NVCAM of claim 5, wherein the matching means includes a seventh switching means.

Claim 11

The multiple-valued NVCAM of claim 5, wherein the first-seventh switching means are NMOS transistors.

Claim 12

The multiple-valued NVCAM of claim 4, wherein the m ferroelectric capacitors of one cell are charged by different voltages of "1" data on the respective bit line.

Claim 13

A multiple-valued NVCAM comprising: a j row by k column memory cell array, the cells of each column being connected to a bit line, m drive lines and m word lines, each cell including m FETs and m ferroelectric capacitors, the ferroelectric capacitors of one cell being charged by different voltages of "1" data on the bit line, one FET and the respective ferroelectric capacitor being connected in series between the bit line and the respective drive line, the FET being turned on and off by a signal on the respective word line, j, k and m being integers, the capacitances of the m ferroelectric capacitors of one cell being different; and data sensing means for comparing the data stored in the cells to reference data, the data sensing means comprising: data acquisition means for acquiring the comparison results; and j data comparison means, each data comparison means being connected to the cells of the respective column and the data acquire means, each data comparison means comparing the data stored in the cells of the respective column to the reference data to provide comparison results to the data acquire means.

Claim 14

A multiple-valued NVCAM comprising: a j row by k column memory cell array, the cells of each column being connected to a bit line, m drive lines and m word lines, each cell including m FETs and m ferroelectric capacitors, the ferroelectric capacitors of one cell being charged by different voltages of "1" data on the bit line, one FET and the respective ferroelectric capacitor being connected in series between the bit line and the respective drive line, the FET being turned on and off by a signal on the respective word line, j, k and m being integers, the capacitances of the m ferroelectric capacitors of one cell being different; and data sensing means for comparing the data stored in the cells to reference data, the data sensing means comprising: data acquisition means for acquiring the comparison results; and j data comparison means, each data comparison means being connected to the cells of the respective column and the data acquire means, each data comparison means comparing the data stored in the cells of the respective column to the reference data to provide comparison results to the data acquire means.

Claim 15

The multiple-valued NVCAM of claim 11, wherein m is two and the NVCAM stores four-valued data.