US5828615A
Expired / Lapsed
US
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Reference potential generator and a semiconductor memory device having the same
Assignee: Panasonic Holdings Corp
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Filing: 1997-01-08
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Granted: 1998-10-27
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Expires: 2017-01-08
Abstract
Abstract A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.
Inventors
- 👤 Toshio Mukunoki
- 👤 Hiroshige Hirano
- 👤 George Nakane
- 👤 Tetsuji Nakakuma
- 👤 Tatsumi Sumi
- 👤 Nobuyuki Moriwaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:28
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C5/147; G11C7/00; G11C7/06; G11C7/14; G11C7/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
198 words
A semiconductor memory device comprising: a memory cell; a first bit line and a second bit line operative to read out data stored in said memory cell; a third bit line and a fourth bit line for providing a reference potential; a reference potential generating means which comprises a charge supplying means operative for supplying a charge to said third and fourth bit lines; first connecting means having a switching function for coupling said third bit line and said charge supplying means and for coupling said fourth bit line and said charge supplying means; and a second connecting means having a switching function for coupling said third bit line and said fourth bit line; and a sense amplifier which utilizes said first bit line and said second bit line as its input and output lines, wherein said memory cell and said charge supplying means comprise circuits in which capacitors of same design are incorporated, and said second connecting means is operative for equalizing the potential of said third and fourth bit lines by connecting said third and fourth bit lines to each other after said charge supplying means supplies a charge to said third and fourth bit lines.
Claim 2
Dependent Claim
198 words
A semiconductor memory device comprising: a memory cell; a first bit line and a second bit line operative to read out data stored in said memory cell; a third bit line and a fourth bit line for providing a reference potential; a reference potential generating means which comprises a charge supplying means operative for supplying a charge to said third and fourth bit lines; first connecting means having a switching function for coupling said third bit line and said charge supplying means and for coupling said fourth bit line and said charge supplying means; and a second connecting means having a switching function for coupling said third bit line and said fourth bit line; and a sense amplifier which utilizes said first bit line and said second bit line as its input and output lines, wherein said memory cell and said charge supplying means comprise circuits in which capacitors of same design are incorporated, and said second connecting means is operative for equalizing the potential of said third and fourth bit lines by connecting said third and fourth bit lines to each other after said charge supplying means supplies a charge to said third and fourth bit lines.
Claim 3
Dependent Claim
28 words
The semiconductor memory device according to claim 1, wherein said capacitors consist of a capacitor in which "H" is written and a capacitor in which "L" is written.
Claim 4
Dependent Claim
15 words
The semiconductor memory device according to claim 1, wherein said capacitors consist of ferroelectric capacitors.
Claim 5
Dependent Claim
14 words
The semiconductor memory device according to claim 2, wherein said capacitors of ferroelectric capacitors.
Claim 6
Dependent Claim
207 words
A semiconductor memory device comprising: a memory cell; a first bit line and a second bit line operative to read out data stored in said memory cell; a third bit line and a fourth bit line for providing a reference potential; and a reference potential generating means which comprises a first charge supplying means operative for supplying a charge to said third bit line; a second charge supplying means operative for supplying a charge to said fourth bit line; a first connecting means having a switching function for coupling said third bit line and said first charge supplying means; a second connecting means having a switching function for coupling said fourth bit line and said second charge supplying means; and a third connecting means having a switching function for coupling said third bit line and said fourth bit line; wherein said memory cell, said first charge supplying means and said second charge supplying means comprise circuits including capacitors of same design and said first charge supplying means supplies a "H" charge which is same as a charge to write "1" to said memory means and said second charge supplying means supplies a "L" charge which is same as a charge to write "0" to said memory means.
Claim 7
Dependent Claim
207 words
A semiconductor memory device comprising: a memory cell; a first bit line and a second bit line operative to read out data stored in said memory cell; a third bit line and a fourth bit line for providing a reference potential; and a reference potential generating means which comprises a first charge supplying means operative for supplying a charge to said third bit line; a second charge supplying means operative for supplying a charge to said fourth bit line; a first connecting means having a switching function for coupling said third bit line and said first charge supplying means; a second connecting means having a switching function for coupling said fourth bit line and said second charge supplying means; and a third connecting means having a switching function for coupling said third bit line and said fourth bit line; wherein said memory cell, said first charge supplying means and said second charge supplying means comprise circuits including capacitors of same design and said first charge supplying means supplies a "H" charge which is same as a charge to write "1" to said memory means and said second charge supplying means supplies a "L" charge which is same as a charge to write "0" to said memory means.
Claim 8
Dependent Claim
16 words
A semiconductor memory device according to claim 5, wherein said capacitors are consisted of ferroelectric capacitors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |