US6043690A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bidirectional follower for driving a capacitive load
Assignee: Aptina Imaging Corp
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Filing: 1998-03-10
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Granted: 2000-03-28
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Expires: 2018-03-10
Abstract
Abstract A bidirectional source follower system includes an N channel transistor and P channel transistor which conduct in opposite ways. The n channel transistor is connected to quickly source current, however is relatively inefficient at sinking current. In contrast, the P channel transistor can sink current very quickly but is bad at source current. The two devices are connected together in a way which allows advantageous features of both.
Inventors
- 👤 Alexander Krymski
- 👤 Sandor Barna
- 👤 Barmak Mansoorian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:36
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
137 words
A source follower buffer circuit comprising: a first source follower circuit part including a first transistor and a second transistor, said first transistor receiving an input signal, and said second transistor producing a biasing signal based on said input signal; and a second source follower circuit part, producing an output signal, and including a third transistor having a first conductivity type and receiving said input signal, said third transistor connected to source current to a capacitive load when said input signal is increased, and a fourth transistor having a conductivity type opposite to said first conductivity type and connected to sink current from said capacitive load, one of said first and second transistors operating to set a bias level of said fourth transistor, wherein said first source follower circuit part is not affected by said capacitive load.
Claim 2
Dependent Claim
137 words
A source follower buffer circuit comprising: a first source follower circuit part including a first transistor and a second transistor, said first transistor receiving an input signal, and said second transistor producing a biasing signal based on said input signal; and a second source follower circuit part, producing an output signal, and including a third transistor having a first conductivity type and receiving said input signal, said third transistor connected to source current to a capacitive load when said input signal is increased, and a fourth transistor having a conductivity type opposite to said first conductivity type and connected to sink current from said capacitive load, one of said first and second transistors operating to set a bias level of said fourth transistor, wherein said first source follower circuit part is not affected by said capacitive load.
Claim 3
Dependent Claim
41 words
A circuit as in claim 1 wherein said first source follower circuit part includes a P channel transistor and an N channel transistor, and said second source follower circuit part also includes a P channel transistor and an N channel transistor.
Claim 4
Dependent Claim
19 words
A circuit as in claim 1 further comprising a current reference, connected to said first source follower circuit part.
Claim 5
Dependent Claim
24 words
A circuit as in claim 2 wherein said N channel transistors are the same size and said P channel transistors are the same size.
Claim 6
Dependent Claim
31 words
The circuit as in claim 2 wherein the transistors in said second source follower circuit part are scaled to be larger than corresponding transistors in said first source follower circuit part.
Claim 7
Dependent Claim
134 words
A source follower circuit, comprising: a first output transistor, having a first conductivity type and receiving an input signal, said first output transistor connected to source current to a capacitive load when an input signal is increased, said first output transistor operating in an active region; a second output transistor, having a second conductivity type opposite to said first conductivity type and connected to sink current from said capacitive load, said second output transistor operating in its active region; a bias transistor, connected to one of said first and second output transistors, and operating to provide a bias level of said one transistor; an input transistor receiving said input signal, said input transistor operatively connected to said bias transistor to allow current from said capacitive load to quickly sink through said second output transistor.
Claim 8
Dependent Claim
134 words
A source follower circuit, comprising: a first output transistor, having a first conductivity type and receiving an input signal, said first output transistor connected to source current to a capacitive load when an input signal is increased, said first output transistor operating in an active region; a second output transistor, having a second conductivity type opposite to said first conductivity type and connected to sink current from said capacitive load, said second output transistor operating in its active region; a bias transistor, connected to one of said first and second output transistors, and operating to provide a bias level of said one transistor; an input transistor receiving said input signal, said input transistor operatively connected to said bias transistor to allow current from said capacitive load to quickly sink through said second output transistor.
Claim 9
Dependent Claim
15 words
The circuit as in claim 6 wherein said bias transistor is a diode connected transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |