Self-configuring interface circuitry, including circuitry for identifying a protocol used to send signals to the interface circuitry, and circuitry for receiving the signals using the identified protocol

Claim 2

An integrated circuit having a plurality of terminals for communicating signals with another device, the integrated circuit comprising: interface circuitry configurable to communicate signals with the other device via the plurality of terminals in accordance with any one of a plurality of interface protocols responsive to a mode selection signal; and protocol identifying circuitry coupled to at least one of the plurality of terminals for monitoring at least one time varying signal communicated to the integrated circuit by the other device, and coupled to the interface circuitry for providing the mode selection signal, wherein each of the plurality of interface protocols has a corresponding signature, and the protocol identifying circuitry provides the mode selection signal responsive to detecting an occurrence of any of the signatures in the at least one monitored signal, so that the interface is configured to use the same protocol as that used by the other device to communicate the signals to the integrated circuit.

Claim 3

The integrated circuit of claim 1 further comprising reset circuitry for resetting the protocol identifying circuitry to provide a predetermined mode selection signal.

Claim 4

The integrated circuit of claim 2 wherein the predetermined mode selection signal corresponds to a predetermined one of the plurality of protocols.

Claim 5

The integrated circuit of claim 2, wherein the reset circuitry generates a reset signal responsive to application of power to the integrated circuit, to a signal on a reset terminal, or to a predetermined sequence of signals on the terminals.

Claim 6

The integrated circuit of claim 1, wherein the plurality of terminals comprises at least two terminals, and wherein a signature comprises a predetermined sequence of transitions of the signals on the at least two terminals.

Claim 7

The integrated circuit of claim 5, wherein a predetermined sequence of transitions of signals on the at least two terminals comprises which of the signals on the at least two terminals exhibits a transition first.

Claim 8

The integrated circuit of claim 1, wherein the protocol detection circuitry comprises latch circuits.

Claim 9

The integrated circuit of claim 1, wherein the plurality of terminals comprise chip select, clock, and data input terminals.

Claim 10

The integrated circuit of claim 8, wherein the protocol identifying circuit comprises first and second latches coupled to the chip select and data input terminals respectively.

Claim 11

The integrated circuit of claim 8, wherein the plurality of interface protocols comprises the increment-only, increment/decrement, and SPI protocols.

Claim 12

Circuitry for providing a protocol selection signal in an integrated circuit, wherein the integrated circuit includes a plurality of terminals adapted to receive signals from at least one other device and circuitry to process the received signals in accordance with a protocol selected from a predetermined plurality of protocols responsive to the protocol selection signal, the circuitry comprising: an input path coupled to at least one of the plurality of input terminals, the input path being adapted to receive the signals from the at least one other device; and latching circuitry, coupled to the input path, which monitors the signals from the at least one other device to detect the occurrence of a signature indicative of any one of the plurality of protocols, the latching circuitry providing the mode selection signal corresponding to the protocol indicated by the detected signature.

Claim 13

Circuitry for providing a protocol selection signal in an integrated circuit, wherein the integrated circuit includes a plurality of terminals adapted to receive signals from at least one other device and circuitry to process the received signals in accordance with a protocol selected from a predetermined plurality of protocols responsive to the protocol selection signal, the circuitry comprising: an input path coupled to at least one of the plurality of input terminals, the input path being adapted to receive the signals from the at least one other device; and latching circuitry, coupled to the input path, which monitors the signals from the at least one other device to detect the occurrence of a signature indicative of any one of the plurality of protocols, the latching circuitry providing the mode selection signal corresponding to the protocol indicated by the detected signature.

Claim 14

The circuitry of claim 11, further comprising latching circuitry, including a plurality of latches coupled to the input path and output path, each latch having an input and an output.

Claim 15

The configuration circuitry of claim 12, wherein the output of at least one of the plurality of latches is coupled to the input of at least one of the other latches comprising the plurality of latches.

Claim 18

The method of claim 14, wherein the integrated circuit has an output terminal and circuitry which processes signals for transmission via the output terminal in accordance with the selected one of the plurality of predetermined protocols.

Claim 19

The method of claim 14 wherein the step of analyzing the input signals determines a signature corresponding to one of the increment-only, increment/decrement, and SPI protocols.

Claim 20

The method of claim 14 further comprising the step of repeating the steps of accepting the input signals through the step of selecting one of the plurality of predetermined protocols in sequence.

Claim 21

The method of claim 14, further comprising the step of fixing the enable signal to the selected enable signal, such that the enable signal remains constant until the interface circuit is reset.

Claim 24

The method of claim 19, wherein the steps of monitoring the at least one signal, altering the state of the configuration circuit, and providing the configuration signal are repeated sequentially.

Claim 25

The method of claim 19 further comprising the step of preventing further alterations in the state of the configuration circuit after the step of altering the state of the configuration circuit.

Claim 26

The method of claim 19 wherein the step of determining a signature comprises determining a signature for one of the increment-only, increment/decrement, and SPI protocols.

Claim 27

An interface circuit for an integrated circuit having a plurality of input terminals, the interface circuit comprising: means, coupled to the plurality of input terminals, for processing signals received via the plurality of input terminals in accordance with a selected one of a plurality of interface protocols as determined by a mode selection signal; and means, coupled to at least one of the plurality of input terminals for monitoring at least one time varying signal received thereon, and coupled to the processing circuitry for providing the mode selection signal responsive to the detection of a signature within the at least one monitored signal on the at least one input terminal indicative of a specific one of the plurality of protocols.

Claim 28

An interface circuit for an integrated circuit having a plurality of input terminals, the interface circuit comprising: means, coupled to the plurality of input terminals, for processing signals received via the plurality of input terminals in accordance with a selected one of a plurality of interface protocols as determined by a mode selection signal; and means, coupled to at least one of the plurality of input terminals for monitoring at least one time varying signal received thereon, and coupled to the processing circuitry for providing the mode selection signal responsive to the detection of a signature within the at least one monitored signal on the at least one input terminal indicative of a specific one of the plurality of protocols.

Claim 29

The interface circuit of claim 23 further comprising means for resetting the protocol identifying circuitry to provide a predetermined mode selection signal corresponding to a predetermined one of the plurality of protocols.

Claim 30

The interface circuit of claim 23, wherein the means for resetting the protocol identifying circuitry comprises a power on reset means.

Claim 31

The interface circuit of claim 23, wherein the plurality of input terminals comprises at least two input terminals, and wherein the means for monitoring signals comprises means for monitoring transitions in signals on the at least two input terminals.

Claim 32

The interface circuit of claim 26, wherein the means for monitoring transitions in signals on the at least two input terminals comprises means for determining the sequence of the transitions in the signals on the at least two input terminals.

Claim 33

The interface circuit of claim 23, wherein the means for providing the mode selection signal comprises latch means.

Claim 34

The interface circuit of claim 23, wherein the input terminals comprise chip select, clock, and data input terminals.

Claim 35

The interface circuit of claim 29, wherein the means for providing the mode selection signal comprises first and second latching means coupled to the chip select and data input terminals respectively.

Claim 36

The interface circuit of claim 29, wherein the plurality of protocols comprises at least one of the increment-only, increment/decrement, and SPI protocols.

Claim 37

Configuration circuitry for providing a mode selection signal to an interface circuit of an integrated circuit for configuring the interface circuit to use a selected one of a plurality of interface protocols, wherein the integrated circuit includes a plurality of terminals adapted to receive signals from at least one other device, the configuration circuitry comprising: input means coupled to at least one of the plurality of input terminals, the input means being adapted to receive input signals; an output means coupled to the interface circuitry; and latching means, coupled to the input means which monitors the input signals for a signature indicative of a specific one of the plurality of protocols, the latching means also being coupled to the output means to provide the mode selection signal to the interface circuitry.

Claim 38

Configuration circuitry for providing a mode selection signal to an interface circuit of an integrated circuit for configuring the interface circuit to use a selected one of a plurality of interface protocols, wherein the integrated circuit includes a plurality of terminals adapted to receive signals from at least one other device, the configuration circuitry comprising: input means coupled to at least one of the plurality of input terminals, the input means being adapted to receive input signals; an output means coupled to the interface circuitry; and latching means, coupled to the input means which monitors the input signals for a signature indicative of a specific one of the plurality of protocols, the latching means also being coupled to the output means to provide the mode selection signal to the interface circuitry.

Claim 39

The configuration circuitry of claim 32, wherein the latching means comprises a plurality of latches coupled to the input means and output means, each latch having an input and an output.

Claim 40

The configuration circuitry of claim 33, wherein the output of at least one of the plurality of latches is coupled to the input of at least one of the other latches comprising the plurality of latches.

Claim 41

Interface circuitry for an integrated circuit having an input terminal, wherein the interface circuitry is operable in accordance with a selected one of a predetermined plurality of protocols responsive to a mode selection signal, comprising: decoding circuitry which provides a selected enable signal from a plurality of enable signals corresponding to the predetermined plurality of protocols, responsive to the mode selection signal; and protocol implementing circuits coupled to the input terminal and to the decoding circuitry, each protocol implementing circuit processing signals received at the input terminal in accordance with at least one of the predetermined plurality of protocols, wherein each protocol implementing circuit is enabled responsive to the selected enable signal.

Claim 42

Interface circuitry for an integrated circuit having an input terminal, wherein the interface circuitry is operable in accordance with a selected one of a predetermined plurality of protocols responsive to a mode selection signal, comprising: decoding circuitry which provides a selected enable signal from a plurality of enable signals corresponding to the predetermined plurality of protocols, responsive to the mode selection signal; and protocol implementing circuits coupled to the input terminal and to the decoding circuitry, each protocol implementing circuit processing signals received at the input terminal in accordance with at least one of the predetermined plurality of protocols, wherein each protocol implementing circuit is enabled responsive to the selected enable signal.

Claim 43

An interface circuit for an integrated circuit having a plurality of input terminals including chip select, data input, and clock terminals, the interface circuit being operable in accordance with any one of the increment-only, up/down, and SPI interface protocols, the interface circuit comprising: interface circuitry coupled to the plurality of input terminals, wherein the interface circuitry processes signals received via the plurality of input terminals in accordance with one of the increment-only, up/down, and SPI interface protocols as determined by a mode selection signal; protocol identifying circuitry comprising latch circuits coupled to at least the data input terminal for monitoring signals thereon, and coupled to the interface circuitry for providing the mode selection signal responsive to the detection of a signature within the monitored signals on the data input terminal indicative of a specific one of the increment-only, up/down, and SPI interface protocols; and reset circuitry for resetting the protocol identifying circuitry to provide a predetermined mode selection signal.

Claim 44

An interface circuit for an integrated circuit having a plurality of input terminals including chip select, data input, and clock terminals, the interface circuit being operable in accordance with any one of the increment-only, up/down, and SPI interface protocols, the interface circuit comprising: interface circuitry coupled to the plurality of input terminals, wherein the interface circuitry processes signals received via the plurality of input terminals in accordance with one of the increment-only, up/down, and SPI interface protocols as determined by a mode selection signal; protocol identifying circuitry comprising latch circuits coupled to at least the data input terminal for monitoring signals thereon, and coupled to the interface circuitry for providing the mode selection signal responsive to the detection of a signature within the monitored signals on the data input terminal indicative of a specific one of the increment-only, up/down, and SPI interface protocols; and reset circuitry for resetting the protocol identifying circuitry to provide a predetermined mode selection signal.

Claim 45

The interface circuit of claim 36 wherein the predetermined mode selection signal corresponds to a predetermined one of the increment-only, up/down, and SPI interface protocols.