US6034916A
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US
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Data masking circuits and methods for integrated circuit memory devices, including data strobe signal synchronization
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-10-14
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Granted: 2000-03-07
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Expires: 2018-10-14
Abstract
Abstract External data and an external data masking signal are synchronized to a data strobe signal rather than a clock signal in an SDRAM. Since both the data masking signal and the data are synchronized with the data strobe signal, they can react in the same way to conditions such as voltage, temperature and process variations. Accordingly, the sampling window of the data can be larger and the number of pins for inputting the data masking signal need not increase. More specifically, integrated circuit memory devices include a memory cell array and an address buffer that buffers address data for the memory cell array in response to a clock signal. A command buffer buffers read and write commands for the memory cell array in response to the clock signal. The data input and output buffer buffers data for the memory cell array in response to a data strobe signal that is different from the clock signal. A data masking buffer buffers the data masking signal that masks the data in response to the data strobe signal. A circuit is responsive to the address buffer, the command buffer, the data input and output buffer and the data masking buffer, to produce first and second masked data on first and second data lines of the memory cell array.
Inventors
- 👤 Jae-Hyeong Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:34
CPC Classifications
G; G11; G11C; G11C29/00; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
98 words
An integrated circuit memory device comprising: a memory cell array; an address buffer that buffers address data for the memory cell array in response to a clock signal; a command buffer that buffers read and write commands for the memory cell array in response to the clock signal; a data input and output buffer that buffers data for the memory cell array in response to a data strobe signal that is different from the clock signal; and a data masking buffer that buffers a data masking signal that masks the data in response to the data strobe signal.
Claim 2
Dependent Claim
98 words
An integrated circuit memory device comprising: a memory cell array; an address buffer that buffers address data for the memory cell array in response to a clock signal; a command buffer that buffers read and write commands for the memory cell array in response to the clock signal; a data input and output buffer that buffers data for the memory cell array in response to a data strobe signal that is different from the clock signal; and a data masking buffer that buffers a data masking signal that masks the data in response to the data strobe signal.
Claim 3
Dependent Claim
52 words
The integrated circuit memory device according to claim 1 further comprising: a circuit that is responsive to the address buffer, the command buffer, the data input and output buffer and the data masking buffer, to produce first and second masked data on first and second data lines of the memory cell array.
Claim 4
Dependent Claim
110 words
The integrated circuit memory device according to claim 2, wherein the circuit comprises: a column select line signal generating portion that is responsive to the address buffer, the command buffer and the data masking buffer to generate first and second column select line signals; a data transmitting portion that is responsive to the data input and output buffer to generate first and second data; and a column selecting portion that transmits the first and second data to the first and second data lines in response to the respective first and second column select line signals, to produce the first and second masked data on the first and second data lines.
Claim 5
Dependent Claim
111 words
The integrated circuit memory device according to claim 2, wherein the circuit comprises: a column select line signal generating portion that is responsive to the address buffer and the command buffer to generate first and second column select line signals; a data transmitting portion that is responsive to the data input and output buffer and the data masking buffer to generate first and second data; and a column selecting portion that transmits the first and second data to the first and second data lines in response to the respective first and second column select line signals, to produce the first and second masked data on the first and second data lines.
Claim 6
Dependent Claim
64 words
The integrated circuit memory device according to claim 3, wherein the column selecting portion comprises: a first transistor that is gated by the first column select line signal, to produce the first masked data on the first data line; and a second transistor that is gated by the second column select line signal, to produce the second masked data on the second data line.
Claim 7
Dependent Claim
64 words
The integrated circuit memory device according to claim 4, wherein the column selecting portion comprises: a first transistor that is gated by the first column select line signal, to produce the first masked data on the first data line; and a second transistor that is gated by the second column select line signal, to produce the second masked data on the second data line.
Claim 8
Dependent Claim
90 words
An integrated circuit memory device comprising: a memory cell array; first means for buffering address data for the memory cell array in response to a clock signal; second means for buffering read and write commands for the memory cell array in response to the clock signal; third means for buffering data for the memory cell array in response to a data strobe signal that is different from the clock signal; and fourth means for buffering a data masking signal that masks the data in response to the data strobe signal.
Claim 9
Dependent Claim
90 words
An integrated circuit memory device comprising: a memory cell array; first means for buffering address data for the memory cell array in response to a clock signal; second means for buffering read and write commands for the memory cell array in response to the clock signal; third means for buffering data for the memory cell array in response to a data strobe signal that is different from the clock signal; and fourth means for buffering a data masking signal that masks the data in response to the data strobe signal.
Claim 10
Dependent Claim
42 words
The integrated circuit memory device according to claim 7 further comprising: means for producing first and second masked data on first and second data lines of the memory cell array in response to the first, second, third and fourth means for buffering.
Claim 11
Dependent Claim
95 words
The integrated circuit memory device according to claim 8, wherein the means for producing comprises: fifth means for generating first and second column select line signals in response to the first, second and fourth means for buffering; second means for generating first and second data in response to the third means for buffering; and means for transmitting the first and second data to the first and second data lines in response to the respective fifth and sixth means for generating, to produce the first and second masked data on the first and second data lines.
Claim 12
Dependent Claim
96 words
The integrated circuit memory device according to claim 8, wherein the means for producing comprises: first means for generating first and second column select line signals in response to the first and second means for buffering; second means for generating first and second data in response to the third and fourth means for buffering; and means for transmitting the first and second data to the first and second data lines in response to the respective fifth and sixth means for generating, to produce the first and second masked data on the first and second data lines.
Claim 13
Dependent Claim
89 words
A data masking method for an integrated circuit memory device including a memory cell array, the method comprising the steps of: buffering address data for the memory cell array in response to a clock signal; buffering read and write commands for the memory cell array in response to the clock signal; buffering data for the memory cell array in response to a data strobe signal that is different from the clock signal; and buffering a data masking signal that masks the data in response to the data strobe signal.
Claim 14
Dependent Claim
89 words
A data masking method for an integrated circuit memory device including a memory cell array, the method comprising the steps of: buffering address data for the memory cell array in response to a clock signal; buffering read and write commands for the memory cell array in response to the clock signal; buffering data for the memory cell array in response to a data strobe signal that is different from the clock signal; and buffering a data masking signal that masks the data in response to the data strobe signal.
Claim 15
Dependent Claim
48 words
The method according to claim 11 further comprising the step of: producing first and second masked data on first and second data lines of the memory cell array in response to the address data, the read and write commands, the data and the data masking signal so buffered.
Claim 16
Dependent Claim
93 words
The method according to claim 12, wherein the producing step comprises the steps of: generating first and second column select line signals in response to the address data, the read and write commands and the data masking signal so buffered; generating first and second data in response to the data so buffered; and transmitting the first and second data to the first and second data lines in response to the respective first and second column select line signals, to produce the first and second masked data on the first and second data lines.
Claim 17
Dependent Claim
94 words
The method according to claim 12, wherein the producing step comprises the steps of: generating first and second column select line signals in response to the address data and the read and write commands so buffered; generating first and second data in response to the data and the data masking signal so buffered; and transmitting the first and second data to the first and second data lines in response to the respective first and second column select line signals, to produce the first and second masked data on the first and second data lines.
Claim 18
Dependent Claim
131 words
A data masking circuit for an integrated circuit memory device, comprising: a column select line signal generating portion that generates first and second column select line signals from an address and a write command that are synchronized with a clock signal; a data transmitting portion that transmits first and second data from data that is synchronized with a data strobe signal that is different from the clock signal, at least one of the column select line signal generating portion and the data transmitting portion also being responsive to a data masking signal that is synchronized with the data strobe signal; and a column selecting portion that transmits the first and second data to respective first and second data lines in response to the respective first and second column select line signals.
Claim 19
Dependent Claim
131 words
A data masking circuit for an integrated circuit memory device, comprising: a column select line signal generating portion that generates first and second column select line signals from an address and a write command that are synchronized with a clock signal; a data transmitting portion that transmits first and second data from data that is synchronized with a data strobe signal that is different from the clock signal, at least one of the column select line signal generating portion and the data transmitting portion also being responsive to a data masking signal that is synchronized with the data strobe signal; and a column selecting portion that transmits the first and second data to respective first and second data lines in response to the respective first and second column select line signals.
Claim 20
Dependent Claim
53 words
The data masking circuit according to claim 15, wherein the column select line signal generating portion generates the first and second column select line signals from the address and the write command that are synchronized with a clock signal and from the data masking signal that is synchronized with the data strobe signal.
Claim 21
Dependent Claim
35 words
The data masking circuit according to claim 15, wherein the data transmitting portion transmits the first and second data from the data and the data masking signal that are synchronized with a data strobe signal.
Claim 22
Dependent Claim
21 words
The data masking circuit according to claim 15 further comprising an address buffer that synchronizes the address with the clock signal.
Claim 23
Dependent Claim
22 words
The data masking circuit according to claim 15 further comprising a command buffer that synchronizes the write command with the clock signal.
Claim 24
Dependent Claim
25 words
The data masking circuit according to claim 15 further comprising a data input and output buffer that synchronizes the data with the data strobe signal.
Claim 25
Dependent Claim
25 words
The data masking circuit according to claim 15 further comprising a data masking buffer that synchronizes the data masking signal with the data strobe signal.
Claim 26
Dependent Claim
63 words
The data masking circuit according to claim 14, wherein the column selecting portion comprises: a first transistor that is gated by the first column select line signal, to produce the first masked data on the first data line; and a second transistor that is gated by the second column select line signal, to produce the second masked data on the second data line.
Claim 27
Dependent Claim
115 words
A data masking apparatus for an integrated circuit memory device, comprising: first means for generating first and second column select line signals from an address and a write command that are synchronized with a clock signal; second means for transmitting first and second data from data that is synchronized with a data strobe signal that is different from the clock signal, at least one of the first and second means also being responsive to a data masking signal that is synchronized with the data strobe signal; and third means for transmitting the first and second data to respective first and second data lines in response to the respective first and second column select line signals.
Claim 28
Dependent Claim
115 words
A data masking apparatus for an integrated circuit memory device, comprising: first means for generating first and second column select line signals from an address and a write command that are synchronized with a clock signal; second means for transmitting first and second data from data that is synchronized with a data strobe signal that is different from the clock signal, at least one of the first and second means also being responsive to a data masking signal that is synchronized with the data strobe signal; and third means for transmitting the first and second data to respective first and second data lines in response to the respective first and second column select line signals.
Claim 29
Dependent Claim
49 words
The data masking apparatus according to claim 23, wherein the first means generates the first and second column select line signals from the address and the write command that are synchronized with a clock signal and from the data masking signal that is synchronized with the data strobe signal.
Claim 30
Dependent Claim
34 words
The data masking apparatus according to claim 23, wherein the second means transmits the first and second data from the data and the data masking signal that are synchronized with a data strobe signal.
Claim 31
Dependent Claim
19 words
The data masking apparatus according to claim 23 further comprising means for synchronizing the address with the clock signal.
Claim 32
Dependent Claim
20 words
The data masking apparatus according to claim 23 further comprising means for synchronizing the write command with the clock signal.
Claim 33
Dependent Claim
20 words
The data masking apparatus according to claim 23 further comprising means for synchronizing the data with the data strobe signal.
Claim 34
Dependent Claim
22 words
A data masking apparatus according to claim 23 further comprising means for synchronizing the data masking signal with the data strobe signal.
Claim 35
Dependent Claim
132 words
A data masking method for an integrated circuit memory device, the method comprising the steps of: synchronizing an address and a write command with a clock signal; synchronizing data and a data masking signal with a data strobe signal that is different from the clock signal; generating first and second column select line signals in response to the address and the write command that are synchronized; generating first and second data that is synchronized with rising and falling edges of the data strobe signal, respectively, in response to the data that are synchronized; and transferring the first and second data to first and second data lines in response to the respective first and second column select line signals, to produce first and second masked data on the first and second data lines.
Claim 36
Dependent Claim
132 words
A data masking method for an integrated circuit memory device, the method comprising the steps of: synchronizing an address and a write command with a clock signal; synchronizing data and a data masking signal with a data strobe signal that is different from the clock signal; generating first and second column select line signals in response to the address and the write command that are synchronized; generating first and second data that is synchronized with rising and falling edges of the data strobe signal, respectively, in response to the data that are synchronized; and transferring the first and second data to first and second data lines in response to the respective first and second column select line signals, to produce first and second masked data on the first and second data lines.
Claim 37
Dependent Claim
77 words
The method according to claim 30, wherein the step of generating first and second column select line signals in response to the address and the write command that are synchronized comprises the step of generating first and second column select line signals that are masked in response to the address and the write command that are synchronized with the clock signal and the first and second data masking signal that is synchronized with the data strobe signal.
Claim 38
Dependent Claim
76 words
The method according to claim 30, wherein the step of generating first and second data that is synchronized with rising and falling edges of the data strobe signal, respectively, in response to the data that are synchronized comprises the step of generating first and second data that is masked by the data masking signal and is synchronized with rising and falling edges of the data strobe signal, respectively, in response to the data that are synchronized.
Claim 39
Dependent Claim
45 words
The method according to claim 30, wherein the step of synchronizing the address and the write command with the clock signal comprises the steps of: buffering the address in response to the clock signal; and buffering the write command in response to the clock signal.
Claim 40
Dependent Claim
59 words
The method according to claim 30, wherein the step of synchronizing data and the data masking signal with the data strobe signal comprises the steps of: buffering data in response to the data strobe signal that is different from the clock signal; and buffering the data masking signal that masks the data in response to the data strobe signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |