US6032356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer-level test and burn-in, and semiconductor process
Assignee: FormFactor Inc
•
Filing: 1997-04-15
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Granted: 2000-03-07
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Expires: 2017-04-15
Abstract
Abstract Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.
Inventors
- 👤 Benjamin N. Eldridge
- 👤 Gary W. Grube
- 👤 Igor Y. Khandros
- 👤 Gaetan L. Mathieu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:44
CPC Classifications
H; H05; H05K; H05K7/00; H05K7/02; H05K7/10; H05K7/1053; H05K7/1061; H05K7/1069; B; B23; B23K; B23K1/00; B23K1/0008; B23K20/00; B23K20/002; B23K20/004; C; C23; C23C; C23C18/00; C23C18/16; C23C18/1601; C23C18/1603; C23C18/1605; C23C18/1633; C23C18/1646; C23C18/165; C25; C25D; C25D7/00; C25D7/12; C25D7/123; G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07342; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H05K3/00; H05K3/30; H05K3/306; H05K3/308; H05K3/32; H05K3/325; H05K3/326; H05K3/34; H05K3/341; H05K3/3421; H05K3/3426; H05K3/40; H05K3/4007; H05K3/4015; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10P74/00; H10P74/23; H10W; H10W70/00; H10W70/099; H10W72/00; H10W72/01; H10W72/0198; H10W72/071; H10W72/075; H10W72/20; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W90/00; H10W90/701; B23K2101/00; B23K2101/36; B23K2101/40; C25D21/00; C25D21/02; C25D5/00; C25D5/22; C25D5/60; C25D5/605; G01R31/2855; G01R31/2856; G01R31/286; G01R31/2863; G01R31/2886; H01; H01R; H01R12/00; H01R12/50; H01R12/51; H01R12/52; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0388; H05K2201/0397; H05K2201/06; H05K2201/068; H05K2201/10; H05K2201/10227; H05K2201/1031; H05K2201/10318; H05K2201/10378; H05K2201/10613; H05K2201/10621; H05K2201/10719; H05K2201/10734; H05K2201/10742; H05K2201/1075; H05K2201/10757; H05K2201/10878; H05K2201/10886; H05K2201/10909; H05K2201/10946; H05K3/10; H05K3/20; H05K3/36; H05K3/368; H05K3/4092; H10W46/00; H10W46/501; H10W70/01; H10W70/05; H10W72/012; H10W72/01204; H10W72/01221; H10W72/01223; H10W72/01225; H10W72/01251; H10W72/01255; H10W72/013; H10W72/01331; H10W72/019; H10W72/072; H10W72/07231; H10W72/07236; H10W72/074; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/07551; H10W72/07554; H10W72/221; H10W72/222; H10W72/223; H10W72/241; H10W72/242; H10W72/251; H10W72/252; H10W72/255; H10W72/29; H10W72/30; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/50; H10W72/521; H10W72/522; H10W72/523; H10W72/531; H10W72/533; H10W72/534; H10W72/541; H10W72/543; H10W72/547; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/555; H10W72/59; H10W72/851; H10W72/853; H10W72/856; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952; H10W90/20; H10W90/22; H10W90/721; H10W90/722; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10S; Y10S977/00; Y10S977/70; Y10S977/701; Y10S977/712; Y10S977/723; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/49147; Y10T29/49149; Y10T29/49169; Y10T29/49171; Y10T29/49204; Y10T29/49208; Y10T29/4922; Y10T29/4981; Y10T29/49812; Y10T428/00; Y10T428/12; Y10T428/12389; Y10T428/12396; Y10T428/12493; Y10T428/12528
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
129 words
Method of exercising semiconductor devices, comprising: fabricating a plurality of resilient interconnection elements directly on a plurality of unsingulated semiconductor dies on a semiconductor wafer each interconnection element having (i) a portion attached to a semiconductor die, (ii) a resilient section, having an elongate springable shape, extending from the portion, and (iii) a contact region remote from the semiconductor die, the interconnection element being free standing and the contact region being depressible towards the semiconductor wafer due to resilient spring action of the resilient section; exercising at least a portion of the unsingulated semiconductor dies by contacting the respective contact regions of at least some of the interconnection elements and electrically accessing the semiconductor dies through the interconnection elements; and then singulating the semiconductor dies from the semiconductor wafer.
Claim 2
Dependent Claim
129 words
Method of exercising semiconductor devices, comprising: fabricating a plurality of resilient interconnection elements directly on a plurality of unsingulated semiconductor dies on a semiconductor wafer each interconnection element having (i) a portion attached to a semiconductor die, (ii) a resilient section, having an elongate springable shape, extending from the portion, and (iii) a contact region remote from the semiconductor die, the interconnection element being free standing and the contact region being depressible towards the semiconductor wafer due to resilient spring action of the resilient section; exercising at least a portion of the unsingulated semiconductor dies by contacting the respective contact regions of at least some of the interconnection elements and electrically accessing the semiconductor dies through the interconnection elements; and then singulating the semiconductor dies from the semiconductor wafer.
Claim 3
Dependent Claim
18 words
Method, according to claim 1, further comprising: performing wafer probing prior to fabricating the plurality of interconnection elements.
Claim 4
Dependent Claim
17 words
Method, according to claim 1, further comprising: performing wafer probing prior to exercising the unsingulated semiconductor dies.
Claim 5
Dependent Claim
54 words
Method, according to claim 1, wherein the step of fabricating the plurality of interconnection elements comprises the steps of: depositing a blanket conductive layer onto the semiconductor die, and providing a patterned masking layer over the blanket conductive layer; mounting elements to the blanket conductive layer; and overcoating the elements with a metallic material.
Claim 6
Dependent Claim
15 words
Method, according to claim 4, further comprising: performing wafer probing prior to mounting the elements.
Claim 7
Dependent Claim
15 words
Method, according to claim 4, further comprising: performing wafer probing prior to overcoating the elements.
Claim 8
Dependent Claim
14 words
Method according to claim 1, further comprising: singulating the semiconductor dies from the wafer.
Claim 9
Dependent Claim
19 words
Method, according to claim 7, further comprising. performing final assembly of the singulated semiconductor dies using the interconnection elements.
Claim 10
Dependent Claim
140 words
Semiconductor process, comprising: mounting resilient contact structures directly to a plurality of semiconductor devices resident on a semiconductor wafer each contact structure having (i) a portion attached to a semiconductor device, (ii) a resilient section, having an elongate springable shape, extending from the portion, and (iii) a contact region remote from the semiconductor device, the contact structure being free standing and the contact region being depressible towards the semiconductor wafer due to resilient spring action of the resilient section; contacting the respective contact regions of at least some of the contact structures; with the resilient contact structures, performing a process selected from the group consisting of test and bum-in to determine which of the plurality of semiconductor devices are operable by electrically accessing the semiconductor dies through the contact structures; and then singulating the semiconductor devices from the semiconductor wafer.
Claim 11
Dependent Claim
140 words
Semiconductor process, comprising: mounting resilient contact structures directly to a plurality of semiconductor devices resident on a semiconductor wafer each contact structure having (i) a portion attached to a semiconductor device, (ii) a resilient section, having an elongate springable shape, extending from the portion, and (iii) a contact region remote from the semiconductor device, the contact structure being free standing and the contact region being depressible towards the semiconductor wafer due to resilient spring action of the resilient section; contacting the respective contact regions of at least some of the contact structures; with the resilient contact structures, performing a process selected from the group consisting of test and bum-in to determine which of the plurality of semiconductor devices are operable by electrically accessing the semiconductor dies through the contact structures; and then singulating the semiconductor devices from the semiconductor wafer.
Claim 12
Dependent Claim
21 words
Semiconductor process, according to claim 9, further comprising: mounting a singulated operable semiconductor devices in an assembly using the contact structures.
Claim 13
Dependent Claim
151 words
Semiconductor process, according to claim 9, wherein: the resilient contact structures are mounted directly to the semiconductor devices by: providing an insulating layer over a patterned metal layer on a surface of the semiconductor devices; providing a plurality of openings in the insulating layer; providing a blanket conductive layer atop the insulating layer; providing a patterned layer of masking material over the blanket conductive layer, said patterned layer of masking material having a plurality of openings aligned with the plurality of openings in the insulating layer; bonding a wire to the blanket conductive layer within each of at least a portion of the openings in the patterned layer of masking material; causing each bonded wire to extend from the surface of the semiconductor die; severing each bonded wire at a distance from the surface of the semiconductor die; and overcoating each severed wire and exposed portions of the blanket conductive layer.
Claim 14
Dependent Claim
20 words
Semiconductor process, according to claim 9, wherein said contact region comprises a contact tip structure joined to said resilient section.
Claim 15
Dependent Claim
17 words
Semiconductor process, according to claim 12, wherein: the contact tip structure is prefabricated on a sacrificial substrate.
Claim 16
Dependent Claim
22 words
Semiconductor process, according to claim 12, further comprising: after joining the contact tip structure to the resilient section, removing the sacrificial substrate.
Claim 17
Dependent Claim
14 words
Semiconductor process, according to claim 13, wherein: the sacrificial substrate is a silicon wafer.
Claim 18
Dependent Claim
20 words
Semiconductor process, according to claim 12, wherein: the contact tip structure comprises at least one layer of a conductive material.
Claim 19
Dependent Claim
69 words
Semiconductor process, according to claim 9, wherein: each resilient contact structure comprises a relatively soft core and a relatively hard overcoat; and the core is formed of a material selected from the group consisting of: gold, aluminum, copper, and their alloys; silver, palladium, platinum; metals or alloys such as metals of the platinum group of elements; and solder constituted from lead, tin, indium, bismuth, cadmium, antimony and their alloys.
Claim 20
Dependent Claim
80 words
Semiconductor process, according to claim 9, wherein: each resilient contact structure comprises a relatively soft core and a relatively hard overcoat; and the overcoat is at least one layer of a material selected from the group consisting of: nickel, and its alloys; copper, cobalt, iron, and their alloys; gold; silver; elements of the platinum group; noble metals; semi-noble metals and their alloys, elements of the platinum group and their alloys; tungsten and molybdenum; tin, lead, bismuth, indium and their alloys.
Claim 21
Dependent Claim
72 words
Semiconductor process, according to claim 9, wherein: each resilient contact structure comprises a relatively soft core and a relatively hard overcoat; and the overcoat is applied to the core using a process selected from the group consisting of deposition of materials out of aqueous solutions; electrolytic plating; electroless plating; chemical vapor deposition (CVD); physical vapor deposition (PVD); and processes causing the deposition of materials through induced disintegration of liquid or solid precursors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |