Self-aligned copper interconnect architecture with enhanced copper diffusion barrier

Claim 1

A method of forming a conductive via between a lower interconnect layer and an upper interconnect layer in a semiconductor device structure, the method comprising: forming a conductive lower diffusion barrier layer on an underlying layer as part of the semiconductor device structure; forming a first layer of copper on the lower diffusion barrier layer; forming a conductive etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper; forming a second layer of copper on the etch stop layer; forming a conductive antireflective diffusion barrier layer on the second copper layer; etching the antireflective diffusion barrier layer, the second copper layer, the etch stop layer, the first copper layer and the lower diffusion barrier layer to define a patterned metal stack and to expose portions of the underlying layer; forming a layer of conductive diffusion barrier material over vertical sidewalls of the patterned metal stack; forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack; planarizing the first dielectric layer to expose an upper surface of the patterned antireflective diffusion barrier layer; etching selected regions of the patterned antireflective diffusion barrier layer and the underlying patterned second copper layer using the etch stop layer as an etch stop, thereby defining spaced-apart copper-based via pillars having a cap of antireflective diffusion barrier material thereon; forming a layer of dielectric diffusion barrier material on vertical sidewalls of the via pillars exposed be the via pillar etch; forming a second dielectric layer such that the second dielectric layer fills gaps between the via pillars; planarizing the second dielectric layer to expose an upper surface of the via pillar caps; and forming a patterned copper upper interconnect layer overlying the exposed via pillar caps, whereby the via pillars form vias between the lower interconnect layer and the upper interconnect layer.

Claim 2

A method of forming a conductive via between a lower interconnect layer and an upper interconnect layer in a semiconductor device structure, the method comprising: forming a conductive lower diffusion barrier layer on an underlying layer as part of the semiconductor device structure; forming a first layer of copper on the lower diffusion barrier layer; forming a conductive etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper; forming a second layer of copper on the etch stop layer; forming a conductive antireflective diffusion barrier layer on the second copper layer; etching the antireflective diffusion barrier layer, the second copper layer, the etch stop layer, the first copper layer and the lower diffusion barrier layer to define a patterned metal stack and to expose portions of the underlying layer; forming a layer of conductive diffusion barrier material over vertical sidewalls of the patterned metal stack; forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack; planarizing the first dielectric layer to expose an upper surface of the patterned antireflective diffusion barrier layer; etching selected regions of the patterned antireflective diffusion barrier layer and the underlying patterned second copper layer using the etch stop layer as an etch stop, thereby defining spaced-apart copper-based via pillars having a cap of antireflective diffusion barrier material thereon; forming a layer of dielectric diffusion barrier material on vertical sidewalls of the via pillars exposed be the via pillar etch; forming a second dielectric layer such that the second dielectric layer fills gaps between the via pillars; planarizing the second dielectric layer to expose an upper surface of the via pillar caps; and forming a patterned copper upper interconnect layer overlying the exposed via pillar caps, whereby the via pillars form vias between the lower interconnect layer and the upper interconnect layer.