Patent US6029061A successfully refreshed from Google Patents.
US6029061A
Expired / Lapsed
US
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Power saving scheme for a digital wireless communications terminal
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-03-11
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Granted: 2000-02-22
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Expires: 2017-03-11
Abstract
Abstract According to the present invention, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the timebase in a low power mode of operation, and at least one processor coupled to the high accuracy clock and the "slow clock" for controlling the modes of operation. In a preferred embodiment, the mobile communications terminal includes a conversion signal processor (CSP), a digital signal processor (DSP), a communications protocol processor, and a radio frequency (RF) segment. The CSP, which includes a plurality of registers, interfaces with the DSP to execute the timing control functions for the terminal. In the normal operating mode, the timebase is maintained from the high accuracy clock. During inactive periods of terminal operation (e.g., in a paging mode), a sleep mode is enabled wherein the high accuracy clock source is disabled, the DSP, CSP, and communications protocol processor are shut down, and the "slow clock" provides the timebase for the terminal while a sleep counter is decremented for a given sleep interval. Upon expiration of the sleep interval or in response to an intervening external event (e.g., a keypad is depressed), a terminal wake-up is initiated so that the high accuracy clock resumes control of the timebase. Because the high accuracy clock and the "slow clock" are not synchronized, the CSP and DSP calibrate the "slow clock" to the high accuracy clock prior to the terminal entering the sleep mode.
Inventors
- 👤 Peter Kohlschmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:09
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0261; H04W52/0287; H04W52/029; H04W52/0293; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
179 words
A clock circuit comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; and a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source.
Claim 2
Dependent Claim
179 words
A clock circuit comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; and a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source.
Claim 3
Dependent Claim
39 words
The clock circuit according to claim 1, wherein said high accuracy clock source is a crystal-based clock and said low power clock source is a crystal-based clock having a lower operating frequency relative to said high accuracy clock source.
Claim 4
Dependent Claim
58 words
The clock circuit according to claim 1, further comprising a digital signal processor coupled to said conversion signal processor, wherein contents of said plurality of registers are mapped to memory locations in said digital signal processor, said digital signal processor and said conversion signal processor being operable to control timing functions of the clock circuit using said registers.
Claim 5
Dependent Claim
37 words
The clock circuit according to claim 3, wherein said digital signal processor is operable to calibrate said low power clock source to said high accuracy clock source using said contents of said accumulator and said multi-function register.
Claim 6
Dependent Claim
27 words
The clock circuit according to claim 4, wherein said digital signal processor being operable to identify a timing relationship based on a resulting value in said accumulator.
Claim 7
Dependent Claim
41 words
The clock circuit according to claim 5, wherein selected functions in said conversion signal processor, said digital signal processor, and said high accuracy clock source are disabled during said second mode, said given time interval being representative of a sleep interval.
Claim 8
Dependent Claim
71 words
The clock circuit according to claim 6, wherein said digital signal processor is responsive to a wake-up signal from said conversion signal processor at the expiration of said sleep interval, said digital signal processor being further operable to update said timebase using said timing relationship and said sleep interval, and said high accuracy clock source being operable to maintain said updated timebase upon said counter being decremented to a zero value.
Claim 9
Dependent Claim
86 words
The clock circuit according to claim 6, wherein said digital signal processor is responsive to a wake-up signal from said conversion signal processor prior to the expiration of said sleep interval, said plurality of registers further comprising a shadow counter, said shadow counter cooperating with said counter to store an actual sleep interval, said digital signal processor being further operable to update said timebase using said timing relationship and said actual sleep interval, and said high accuracy clock source being operable to maintain said updated timebase.
Claim 10
Dependent Claim
197 words
A cellular communications terminal, comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; and a radio frequency segment coupled to said high accuracy clock source and said conversion signal processor; wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to said clock cycles from said low power clock source.
Claim 11
Dependent Claim
197 words
A cellular communications terminal, comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; a conversion signal processor having a plurality of registers including an accumulator and a multi-function register, said conversion signal processor coupled to said high accuracy clock source and said low power clock source, said conversion signal processor being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said conversion signal processor includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; and a radio frequency segment coupled to said high accuracy clock source and said conversion signal processor; wherein said accumulator is operable to increment according to clock cycles from said high accuracy clock source while said multi-function register is operable to simultaneously decrement a given calibration time period according to said clock cycles from said low power clock source.
Claim 12
Dependent Claim
40 words
The cellular communications terminal according to claim 9, wherein said high accuracy clock source is a crystal-based clock and said low power clock source is a crystal-based clock having a lower operating frequency relative to said high accuracy clock source.
Claim 13
Dependent Claim
89 words
The cellular communications terminal according to claim 9, further comprising: a digital signal processor coupled to said conversion signal processor, wherein contents of said plurality of registers are mapped to memory locations in said digital signal processor, said digital signal processor and said conversion signal processor being operable to control timing functions of the clock circuit using said registers; and a communications processor coupled to said digital signal processor and to said high accuracy clock source, said communications processor being operable to perform general processing functions of the terminal.
Claim 14
Dependent Claim
38 words
The cellular communications terminal according to claim 11, wherein said digital signal processor is operable to calibrate said low power clock source to said high accuracy clock source using said contents of said accumulator and said multi-function register.
Claim 15
Dependent Claim
28 words
The cellular communications terminal according to claim 12, wherein said digital signal processor being operable to identify a timing relationship based on a resulting value in said accumulator.
Claim 16
Dependent Claim
49 words
The cellular communications terminal according to claim 9, wherein selected functions in said conversion signal processor, said digital signal processor, said communications processor, said radio frequency segment, and said high accuracy clock source are disabled during said second mode, said given time interval being representative of a sleep interval.
Claim 17
Dependent Claim
72 words
The cellular communications terminal according to claim 14, wherein said digital signal processor is responsive to a wake-up signal from said conversion signal processor at the expiration of said sleep interval, said digital signal processor being further operable to update said timebase using said timing relationship and said sleep interval, and said high accuracy clock source being operable to maintain said updated timebase upon said counter being decremented to a zero value.
Claim 18
Dependent Claim
87 words
The cellular communications terminal according to claim 14, wherein said digital signal processor is responsive to a wake-up signal from said conversion signal processor prior to the expiration of said sleep interval, said plurality of registers further comprising a shadow counter, said shadow counter cooperating with said counter to store an actual sleep interval, said digital signal processor being further operable to update said timebase using said timing relationship and said actual sleep interval, and said high accuracy clock source being operable to maintain said updated timebase.
Claim 19
Dependent Claim
132 words
A power saving method, comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; disabling said high accuracy clock source via a programmable processor upon entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing an accumulator according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said accumulator.
Claim 20
Dependent Claim
132 words
A power saving method, comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; disabling said high accuracy clock source via a programmable processor upon entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing an accumulator according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said accumulator.
Claim 21
Dependent Claim
35 words
The power saving method according to claim 17, further comprising the step of disabling selected functions of said programmable processor during said second mode, wherein said given time interval is representative of a sleep interval.
Claim 22
Dependent Claim
62 words
The power saving method according to claim 18, further comprising the steps of: providing a wake-up signal to said programmable processor at the expiration of said sleep interval; calculating an updated timebase in said programmable processor using said timing relationship and said sleep interval; and maintaining said updated timebase using said high accuracy clock source at the expiration of said sleep interval.
Claim 23
Dependent Claim
83 words
The power saving method according to claim 18, further comprising the steps of: providing a wake-up signal to said programmable processor prior to the expiration of said sleep interval; measuring an actual sleep interval based on timing of said wake-up signal being provided to said programmable processor; calculating an updated timebase in said programmable processor using said timing relationship and said actual sleep interval; and maintaining said updated timebase using said high accuracy clock source at the expiration of said actual sleep interval.
Claim 24
Independent Claim
147 words
A method of operating a cellular communications terminal, comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; disabling said high accuracy clock source via a conversion signal processor upon entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing an accumulator in said conversion signal processor according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship using a digital signal processor based on a resulting value in said accumulator.
Claim 25
Independent Claim
147 words
A method of operating a cellular communications terminal, comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; disabling said high accuracy clock source via a conversion signal processor upon entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing an accumulator in said conversion signal processor according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship using a digital signal processor based on a resulting value in said accumulator.
Claim 26
Dependent Claim
39 words
The method according to claim 21, further comprising the step of disabling selected functions of said conversion signal processor and said digital signal processor during said second mode, wherein said given time interval is representative of a sleep interval.
Claim 27
Dependent Claim
62 words
The method according to claim 22, further comprising the steps of: providing a wake-up signal to said digital signal processor at the expiration of said sleep interval; calculating an updated timebase in said digital signal processor using said timing relationship and said sleep interval; and maintaining said updated timebase using said high accuracy clock source at the expiration of said sleep interval.
Claim 28
Dependent Claim
84 words
The method according to claim 22, further comprising the steps of: providing a wake-up signal to said digital signal processor prior to the expiration of said sleep interval; measuring an actual sleep interval based on timing of said wake-up signal being provided to said digital signal processor; calculating an updated timebase in said digital signal processor using said timing relationship and said actual sleep interval; and maintaining said updated timebase using said high accuracy clock source at the expiration of said actual sleep interval.
Claim 29
Dependent Claim
157 words
A clock circuit comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; and a digital device having a first register and a second register coupled to said high accuracy clock source and said low power clock source, said digital device being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode, said digital device includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; wherein said first register is operable to increment according to clock cycles from said high accuracy clock source while said second register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source.
Claim 30
Dependent Claim
157 words
A clock circuit comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; and a digital device having a first register and a second register coupled to said high accuracy clock source and said low power clock source, said digital device being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode, said digital device includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; wherein said first register is operable to increment according to clock cycles from said high accuracy clock source while said second register is operable to simultaneously decrement a given calibration time period according to clock cycles from said low power clock source.
Claim 31
Dependent Claim
25 words
The clock circuit according to claim 25 further comprising said digital device being operable to disable said high accuracy clock source during said second mode.
Claim 32
Dependent Claim
14 words
The clock circuit according to claim 25 wherein said first register is an accumulator.
Claim 33
Dependent Claim
15 words
The clock circuit according to claim 25 wherein said second register is a multifunctional register.
Claim 34
Dependent Claim
16 words
The clock circuit according to claim 25 wherein said digital device is a conversion signal processor.
Claim 35
Dependent Claim
189 words
A cellular communications terminal, comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; a digital device having a first register and a second register, said digital device coupled to said high accuracy clock source and said low power clock source, said digital device being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said digital device includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; and a radio frequency segment coupled to said high accuracy clock source and said digital device; wherein said first register is operable to increment according to clock cycles from said high accuracy clock source while said second register is operable to simultaneously decrement a given calibration time period according to said clock cycles from said low power clock source.
Claim 36
Dependent Claim
189 words
A cellular communications terminal, comprising: at least two asynchronous clock sources, including a high accuracy clock source for maintaining a timebase in a first mode, and a low power clock source for maintaining the timebase in a second mode for a given time interval; a digital device having a first register and a second register, said digital device coupled to said high accuracy clock source and said low power clock source, said digital device being operable to calibrate said low power clock source with said high accuracy clock source prior to entering said second mode and to disable said high accuracy clock source during said second mode, said digital device includes a counter operable to decrement said given time interval according to clock cycles from said low power clock source; and a radio frequency segment coupled to said high accuracy clock source and said digital device; wherein said first register is operable to increment according to clock cycles from said high accuracy clock source while said second register is operable to simultaneously decrement a given calibration time period according to said clock cycles from said low power clock source.
Claim 37
Dependent Claim
26 words
The cellular communication terminal according to claim 30 further comprising said digital device being operable to disable said high accuracy clock source during said second mode.
Claim 38
Dependent Claim
15 words
The cellular communications terminal according to claim 30 wherein said first register is an accumulator.
Claim 39
Dependent Claim
16 words
The cellular communications terminal according to claim 30 wherein said second register is a multifunctional register.
Claim 40
Dependent Claim
17 words
The cellular communications terminal according to claim 30 wherein said digital device is a conversion signal processor.
Claim 41
Dependent Claim
119 words
A power saving method comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing a first register according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said first register.
Claim 42
Dependent Claim
119 words
A power saving method comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing a first register according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said first register.
Claim 43
Dependent Claim
24 words
The power saving method according to claim 35 further comprising the step of disabling said high accuracy clock source upon entering said second mode.
Claim 44
Dependent Claim
15 words
The power saving method according to claim 35 wherein said first register is an accumulator.
Claim 45
Independent Claim
123 words
A method of operating a cellular communications terminal, comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing a first register according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said first register.
Claim 46
Independent Claim
123 words
A method of operating a cellular communications terminal, comprising the steps of: maintaining a timebase in a first mode using a high accuracy clock source; maintaining the timebase in a second mode for a given time interval using a low power clock source; calibrating said low power clock source with said high accuracy clock source prior to entering said second mode; decrementing said given time interval according to clock cycles from said low power clock source; simultaneously incrementing a first register according to clock cycles from said high accuracy clock source while decrementing a given calibration time period according to said clock cycles from said low power clock source; and identifying a timing relationship based on a resulting value in said first register.
Claim 47
Dependent Claim
28 words
The method of operating a cellular communications terminal according to claim 38 further comprising the step of disabling said high accuracy clock source upon entering said second mode.
Claim 48
Dependent Claim
19 words
The method of operating a cellular communications terminal according to claim 38 wherein said first register is an accumulator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-21 | 2003-08-23 | 2004-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-21 | 2007-08-23 | 2008-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-21 | 2011-08-23 | 2012-02-22 | $7700.00 | Window Closed / Lapsed |