US5845204A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for controlling the wakeup logic of a radio receiver in sleep mode
Assignee: LG Electronics Inc
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Filing: 1995-08-11
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Granted: 1998-12-01
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Expires: 2015-08-11
Abstract
Abstract A low-power stop mode "snooze" timer is implemented in the processing unit of a communication system, which runs without the use of the usual crystal-controlled oscillator. The "snooze" timer is implemented by a second oscillator with associated timer circuit. The second oscillator runs continually and feeds a timer which is loaded with a suitable value. The timer, when timed out or expired, will reactivate the main processing functions, thus allowing the successful reception of an external signal from a remote transmission source. To compensate for the inaccuracy of the second oscillator due to its dependence upon voltage, process and temperature, the snooze timer's output is calibrated during the wake-up periods against a timing signal derived from the internal crystal-controlled timing source. This calibration compensates for the inherent frequency instability of the second oscillator and allows a timing signal of sufficient accuracy to be maintained over the stop cycle.
Inventors
- 👤 Mark Chapman
- 👤 Dennis E. Starbuck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:15
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0261; H04W52/0287; H04W52/029; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
301 words
A device for invoking a wakeup logic of a processing unit in an electronic system from a low-power stop mode after a predetermined time period, said electronic system comprising a first oscillator of a predetermined frequency and a first counter for providing internal timing to said electronic system, said electronic system converting itself into said low-power stop mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain non-operational until said stop mode is terminated, comprising: a second oscillator of a nominal predetermined frequency for continuously generating an oscillating signal in said low-power stop mode, said second oscillator being less accurate than said first oscillator, said second oscillator being integrated within said processing unit; a second counter coupled to said second oscillator for counting said oscillating signal to a predetermined count until said second counter expires in said predetermined time period; detection means coupled to said second counter for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising: a calibration means coupled to said second oscillator and to said first oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said first oscillator, after said first oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 2
Independent Claim
301 words
A device for invoking a wakeup logic of a processing unit in an electronic system from a low-power stop mode after a predetermined time period, said electronic system comprising a first oscillator of a predetermined frequency and a first counter for providing internal timing to said electronic system, said electronic system converting itself into said low-power stop mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain non-operational until said stop mode is terminated, comprising: a second oscillator of a nominal predetermined frequency for continuously generating an oscillating signal in said low-power stop mode, said second oscillator being less accurate than said first oscillator, said second oscillator being integrated within said processing unit; a second counter coupled to said second oscillator for counting said oscillating signal to a predetermined count until said second counter expires in said predetermined time period; detection means coupled to said second counter for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising: a calibration means coupled to said second oscillator and to said first oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said first oscillator, after said first oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 3
Dependent Claim
81 words
A device according to claim 1, wherein said calibration means: synchronizing said second counter with said first counter in a normal operating mode; said first counter continuously counting said first oscillator until said second counter has expired; reading said first counter to determine the time it took said second counter to expire; calculating said operating frequency of said second oscillator based on said time it took said second counter to expire and said predetermined count initially set in said second counter.
Claim 4
Independent Claim
290 words
A device for invoking a wakeup logic of a processing device in a packet radio communication system from a low-power stop mode after a predetermined time period, said packet radio communication system comprising a first oscillator of a predetermined frequency and a first counter for providing internal timing to said communication system, said packet radio communication system converting itself into said low-power stop mode after a predetermined period of inactivity, said low-power stop mode causing said packet radio communication system to remain non-operational until said stop mode is terminated, comprising: a second oscillator of a nominal predetermined frequency for continuously generating an oscillating signal in said low-power stop mode; a second counter coupled to said second oscillator for counting said oscillating signal to a predetermined count until said second counter expires in said predetermined time period; detection means coupled to said second counter for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising: a calibration means coupled to said second oscillator and to said first oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said first oscillator, after said first oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 5
Independent Claim
290 words
A device for invoking a wakeup logic of a processing device in a packet radio communication system from a low-power stop mode after a predetermined time period, said packet radio communication system comprising a first oscillator of a predetermined frequency and a first counter for providing internal timing to said communication system, said packet radio communication system converting itself into said low-power stop mode after a predetermined period of inactivity, said low-power stop mode causing said packet radio communication system to remain non-operational until said stop mode is terminated, comprising: a second oscillator of a nominal predetermined frequency for continuously generating an oscillating signal in said low-power stop mode; a second counter coupled to said second oscillator for counting said oscillating signal to a predetermined count until said second counter expires in said predetermined time period; detection means coupled to said second counter for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising: a calibration means coupled to said second oscillator and to said first oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said first oscillator, after said first oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 6
Dependent Claim
82 words
A device according to claim 3, wherein said calibration means: synchronizing said second counter with said first counter in a normal operating mode; said first counter continuously counting said first oscillator until said second counter has expired; reading said first counter to determine the time it took said second counter to expire; calculating said true operating frequency of said second oscillator based on said time it took said second counter to expire and said predetermined count initially set in said second counter.
Claim 7
Dependent Claim
325 words
In a processor-based packet radio interfacing between a data processing unit and a wireless data transceiver, said packet radio comprising a first oscillator and a first timer for providing internal timing and a wakeup logic for invoking said packet radio from a stop mode, said stop mode causing said packet radio to remain non-operational after said packet radio has been inactive in a predetermined period to preserve power, a low-power device for periodically triggering said wakeup logic to invoke said packet radio from said stop mode, comprising: a ring oscillator of a predetermined frequency for continuously generating an oscillating signal in said stop mode, said ring oscillator being integrated with said packet radio; a second counter coupled to said ring oscillator for counting said ring oscillator to a predetermined count when said second counter expires corresponding to a predetermined period for said packet radio to awake from said stop mode; detection means coupled to said second counter for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to trigger said wakeup logic, such that stop mode is terminated after said predetermined period; a calibration means coupled to said ring oscillator and to said first oscillator, said calibration means, operative after said stop mode is terminated, operating said first and second counters to determine an actual time it took said second counter to expire and setting said predetermined period for triggering said wakeup logic according to said actual time of said second oscillator, said calibration means: synchronizing said second counter with said first counter after said stop mode is terminated; said first counter continuously counting said first oscillator until said second counter has expired; reading said first counter to determine the time it took said second counter to expire; calculating an operating frequency of said second oscillator based on said time it took said second counter to expire and said predetermined count initially set in said second counter.
Claim 8
Dependent Claim
325 words
In a processor-based packet radio interfacing between a data processing unit and a wireless data transceiver, said packet radio comprising a first oscillator and a first timer for providing internal timing and a wakeup logic for invoking said packet radio from a stop mode, said stop mode causing said packet radio to remain non-operational after said packet radio has been inactive in a predetermined period to preserve power, a low-power device for periodically triggering said wakeup logic to invoke said packet radio from said stop mode, comprising: a ring oscillator of a predetermined frequency for continuously generating an oscillating signal in said stop mode, said ring oscillator being integrated with said packet radio; a second counter coupled to said ring oscillator for counting said ring oscillator to a predetermined count when said second counter expires corresponding to a predetermined period for said packet radio to awake from said stop mode; detection means coupled to said second counter for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to trigger said wakeup logic, such that stop mode is terminated after said predetermined period; a calibration means coupled to said ring oscillator and to said first oscillator, said calibration means, operative after said stop mode is terminated, operating said first and second counters to determine an actual time it took said second counter to expire and setting said predetermined period for triggering said wakeup logic according to said actual time of said second oscillator, said calibration means: synchronizing said second counter with said first counter after said stop mode is terminated; said first counter continuously counting said first oscillator until said second counter has expired; reading said first counter to determine the time it took said second counter to expire; calculating an operating frequency of said second oscillator based on said time it took said second counter to expire and said predetermined count initially set in said second counter.
Claim 9
Independent Claim
304 words
A method for a processing unit in an electronic system to self-awaken from a low-power stop mode after a predetermined time period, said electronic system comprising a second oscillator of a nominal frequency and a crystal oscillator of a predetermined frequency and a first counter for providing internal timing to said electronic system, said electronic system converting itself into said low-power stop mode from a normal operating mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain non-operational until said stop mode is terminated, comprising the steps of: a) continuously operating said second oscillator to generate an oscillating signal in said low-power stop mode; b) counting said oscillating signals by using a second counter coupled to said second oscillator to a predetermined count when said second counter expires in said predetermined time period; c) detecting by using a detection means coupled to said second counter if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising the step of: d) calibrating by using a calibration means coupled to said second oscillator and to said crystal oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said crystal oscillator, after said crystal oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 10
Independent Claim
304 words
A method for a processing unit in an electronic system to self-awaken from a low-power stop mode after a predetermined time period, said electronic system comprising a second oscillator of a nominal frequency and a crystal oscillator of a predetermined frequency and a first counter for providing internal timing to said electronic system, said electronic system converting itself into said low-power stop mode from a normal operating mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain non-operational until said stop mode is terminated, comprising the steps of: a) continuously operating said second oscillator to generate an oscillating signal in said low-power stop mode; b) counting said oscillating signals by using a second counter coupled to said second oscillator to a predetermined count when said second counter expires in said predetermined time period; c) detecting by using a detection means coupled to said second counter if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising the step of: d) calibrating by using a calibration means coupled to said second oscillator and to said crystal oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said crystal oscillator, after said crystal oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 11
Dependent Claim
91 words
The method according to claim 6, said step of calibrating further comprises the steps of: e) synchronizing said second counter with said first counter in a normal operating mode; f) said first counter continuously counting said crystal oscillator until said second counter has expired; g) reading said first counter to determine the time it took said second counter to expire; h) calculating said true operating frequency of said second oscillator based on said time it took said second counter to expire and said predetermined count initially set in said second counter.
Claim 12
Independent Claim
312 words
A method for a data/voice communication system to self-awaken from a low-power stop mode after a predetermined time period to receive an asynchronous paging signal from a basestation, said data/voice communication system comprising a second oscillator of a nominal frequency and a crystal oscillator of a predetermined frequency and a first counter for providing internal timing to said electronic system, said data/voice communication system converting itself into said low-power stop mode from a normal operating mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain dormant until said stop mode is terminated, comprising the steps of: a) continuously operating said second oscillator to generate an oscillating signal in said low-power stop mode; b) counting said oscillating signals by using a second counter coupled to said second oscillator to a predetermined count when said second counter expires in said predetermined time period; c) detecting by using a detection means coupled to said second counter if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising the step of: d) calibrating by using a calibration means coupled to said second oscillator and to said crystal oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said crystal oscillator, after said crystal oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 13
Independent Claim
312 words
A method for a data/voice communication system to self-awaken from a low-power stop mode after a predetermined time period to receive an asynchronous paging signal from a basestation, said data/voice communication system comprising a second oscillator of a nominal frequency and a crystal oscillator of a predetermined frequency and a first counter for providing internal timing to said electronic system, said data/voice communication system converting itself into said low-power stop mode from a normal operating mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain dormant until said stop mode is terminated, comprising the steps of: a) continuously operating said second oscillator to generate an oscillating signal in said low-power stop mode; b) counting said oscillating signals by using a second counter coupled to said second oscillator to a predetermined count when said second counter expires in said predetermined time period; c) detecting by using a detection means coupled to said second counter if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic, such that said stop mode is terminated after said predetermined time period, further comprising the step of: d) calibrating by using a calibration means coupled to said second oscillator and to said crystal oscillator, said calibration means, operative after said stop mode is terminated, causing said first counter to count using said crystal oscillator, after said crystal oscillator is out of said stop mode, with said second counter also counting, from a predetermined initial count until said second counter expires, using said second oscillator, said calibration means determining an operating frequency of said second oscillator, based on the time it takes said second counter to expire measured by said first counter and said predetermined initial count, and setting said predetermined time period according to said operating frequency of said second oscillator.
Claim 14
Dependent Claim
91 words
The method according to claim 8, said step of calibrating further comprises the steps of: e) synchronizing said second counter with said first counter in a normal operating mode; f) said first counter continuously counting said crystal oscillator until said second counter has expired; g) reading said first counter to determine the time it took said second counter to expire; h) calculating said true operating frequency of said second oscillator based on said time it took said second counter to expire and said predetermined count initially set in said second counter.
Claim 15
Dependent Claim
14 words
A device according to claim 1, wherein said second oscillator is a ring oscillator.
Claim 16
Dependent Claim
14 words
A device according to claim 3, wherein said second oscillator is a ring oscillator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |