Integrated circuit including high transconductance voltage clamp

Claim 2

An integrated circuit including a clamp circuit for limiting the voltage at a circuit node, said clamp circuit comprising a current source coupled to said node, and a clamp transistor having a control terminal and a pair of input/output terminals, one of said input/output terminals being coupled to said node for limiting the voltage at said node when said clamp transistor conducts, said control terminal being responsive to a control signal and said node voltage being a function of said control signal, characterized in that a current amplifier is coupled across said input/output terminals of said clamp transistor, said amplifier comprising a current mirror that includes a diode-connected transistor coupled in series with said clamp transistor, a current gain transistor coupled in parallel with the series combination of said clamp transistor and said diode-connected transistor, the control terminals of said diode-connected transistor and said current gain transistor being coupled to one another.

Claim 3

The invention of claim 1 wherein said transistors are MOSFETs and the gate widths of said clamp transistor and said current gain transistor are much greater than the gate width of said diode-connected transistor.

Claim 4

An integrated circuit including a differential line driver circuit for providing, in one state, current flow through a load in one direction, and, in another state, current flow through the load in the opposite direction, said line driver circuit comprising first and second current sources for delivering current to a load, said sources being coupled to first and second output nodes, first and second switching transistors coupled between said first and second nodes, respectively, and a source of reference potential, first and second clamp transistors for limiting the voltage at said first and second nodes, respectively, first and second current amplifiers coupled in parallel with said first and second clamp transistors, respectively, and control circuitry for closing said first switching transistor in said one state so that current flows from said second current source through said load in one direction, through said second clamp transistor and said second current amplifier to said source of reference potential, and for closing said second switching transistor in said other state so that current flows from said first current source, through said load in the opposite direction, through said first clamp transistor and said first current amplifier to said source of reference potential.

Claim 5

An integrated circuit including a differential line driver circuit for providing, in one state, current flow through a load in one direction, and, in another state, current flow through the load in the opposite direction, said line driver circuit comprising first and second current sources for delivering current to a load, said sources being coupled to first and second output nodes, first and second switching transistors coupled between said first and second nodes, respectively, and a source of reference potential, first and second clamp transistors for limiting the voltage at said first and second nodes, respectively, first and second current amplifiers coupled in parallel with said first and second clamp transistors, respectively, and control circuitry for closing said first switching transistor in said one state so that current flows from said second current source through said load in one direction, through said second clamp transistor and said second current amplifier to said source of reference potential, and for closing said second switching transistor in said other state so that current flows from said first current source, through said load in the opposite direction, through said first clamp transistor and said first current amplifier to said source of reference potential.

Claim 6

The invention of claim 3 wherein each of said current amplifiers comprises a current mirror.

Claim 7

The invention of claim 4 wherein each of said current mirrors comprises a diode-connected transistor coupled in series with said clamp transistor, a current gain transistor coupled in parallel with the series combination of said clamp transistor and said diode-connected transistor, the control terminals of said diode-connected transistor and said current gain transistor being coupled to one another.

Claim 8

The invention of claim 5 wherein said transistors are MOSFETs and the gate widths of said clamp transistor and said current gain transistor are much greater than the gate width of said diode-connected transistor.

Claim 9

The invention of claim 5 wherein said first switching transistor and said first current gain transistor comprise a single, dual-function transistor, and said second switching transistor and said second current gain transistor also form a single, dual-function transistor.

Claim 10

The invention of claim 7 wherein each of said diode-connected transistors includes a switching transistor being coupled between the control terminal and one of the input/output terminals of said diode-connected transistors, the control terminals of said switching transistors and said diode connected transistors being coupled to said control circuitry.