US5625281A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-voltage multi-output current mirror circuit with improved power supply rejection mirrors and method therefor
Assignee: Exar Corp
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Filing: 1995-06-16
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Granted: 1997-04-29
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Expires: 2015-06-16
Abstract
Abstract A circuit technique for improving power supply rejection of current mirror circuits having multiple outputs. An input reference current is preadjusted for error caused by power supply variations and then mirrored through a cascade of current mirror circuits. In one embodiment an opamp loop forces the output of a current mirror circuit to be substantially equal to the reference current. This current is then used in subsequent mirroring stages to obtain various outputs. The circuit eliminates the need for including an error-subtraction transistor at every output.
Inventors
- 👤 Craig N. Lambert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:51
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
133 words
A circuit comprising: a current source providing a reference current (I1); a first current mirror circuit coupled to said current source, said first current mirror circuit having an output current (I2); an error current generator coupled to said first current mirror circuit, said error current generator generating at an output an error current (I err ) representative of the difference between an expected value of (I1) and an actual value of (I1); a second current mirror circuit coupled to said output of said error current generator for replicating said error current (I err ); and a current adjusting circuit coupled to said error current generator and said first current mirror circuit, said current adjusting circuit generating at an output a current substantially equal to said reference current (I1), or a designed multiple thereof.
Claim 2
Dependent Claim
133 words
A circuit comprising: a current source providing a reference current (I1); a first current mirror circuit coupled to said current source, said first current mirror circuit having an output current (I2); an error current generator coupled to said first current mirror circuit, said error current generator generating at an output an error current (I err ) representative of the difference between an expected value of (I1) and an actual value of (I1); a second current mirror circuit coupled to said output of said error current generator for replicating said error current (I err ); and a current adjusting circuit coupled to said error current generator and said first current mirror circuit, said current adjusting circuit generating at an output a current substantially equal to said reference current (I1), or a designed multiple thereof.
Claim 3
Dependent Claim
84 words
The circuit of claim 1 wherein said error current generator comprises: a third current mirror circuit coupled to said first current mirror circuit, said third current mirror circuit having an output current (I3) at an output; and a first reference current mirror transistor coupled to said output of said third current mirror circuit, wherein, said first reference current mirror transistor subtracts an amount of current substantially equal to said input current (I1) from said current (I3) to generate said error current (I err ).
Claim 4
Dependent Claim
114 words
The circuit of claim 2 wherein said current adjusting circuit comprises: a fourth current mirror circuit coupled to said error current generator for duplicating a current substantially equal to said error current (I err ) at an output node; a diode-connected transistor coupled to said output node to clamp a voltage at said output node at one diode drop; and a second reference current mirror transistor coupled to said output node and, wherein, at said output node, an output current of said diode-connected transistor is substantially equal to an uncorrected mirror of said reference current flowing through said second reference current mirror transistor minus said error current flowing through said fourth current mirror circuit.
Claim 5
Dependent Claim
109 words
A circuit comprising: a current source providing a reference current (I1) through a first diode-connected transistor; an amplifier having a first input coupled to said first diode-connected transistor; a current adjust transistor having a control terminal coupled to an output of said amplifier; a current mirror circuit coupled to said current adjust transistor; and a second diode-connected transistor coupled to an output of said current mirror circuit and a second input of said amplifier, wherein, a current through said current adjust transistor is adjusted by said amplifier such that a current flowing through said output of said current mirror is forced to be substantially equal to said reference current.
Claim 6
Dependent Claim
109 words
A circuit comprising: a current source providing a reference current (I1) through a first diode-connected transistor; an amplifier having a first input coupled to said first diode-connected transistor; a current adjust transistor having a control terminal coupled to an output of said amplifier; a current mirror circuit coupled to said current adjust transistor; and a second diode-connected transistor coupled to an output of said current mirror circuit and a second input of said amplifier, wherein, a current through said current adjust transistor is adjusted by said amplifier such that a current flowing through said output of said current mirror is forced to be substantially equal to said reference current.
Claim 7
Dependent Claim
24 words
The circuit of claim 4 wherein said first and second diode-connected transistors are a matched pair of transistors having substantially identical size and layout.
Claim 8
Dependent Claim
33 words
The circuit of claim 5 further comprising a plurality of mirror transistors coupled to said current mirror circuit, each one of said plurality of mirror transistors being coupled to a diode-connected load transistor.
Claim 9
Dependent Claim
12 words
The circuit of claim 5 wherein all transistors are field effect transistors.
Claim 10
Dependent Claim
19 words
The circuit of claim 5 wherein transistors are selectively implemented in field effect transistor technology and bipolar transistor technology.
Claim 11
Dependent Claim
58 words
The circuit of claim 5 wherein said amplifier is an operational amplifier comprising: a differential pair of input transistors having control terminals coupled to said first and second amplifier inputs, respectively; a current source transistor coupled to said differential pair of input transistors; and a pair of load transistors respectively coupled to said differential pair of input transistors.
Claim 12
Independent Claim
94 words
A method for increasing the power supply rejection of current mirror circuits comprising the steps of: (a) generating a reference current through a first transistor; (b) coupling said first transistor to a first input of an amplifier; (c) adjusting a current flowing through a second transistor by applying an output of said amplifier to said second transistor; (d) mirroring said current flowing through said second transistor with a current mirror circuit; (e) coupling said current mirror circuit to a third transistor; and (f) coupling said third transistors to a second input of said amplifier.
Claim 13
Independent Claim
94 words
A method for increasing the power supply rejection of current mirror circuits comprising the steps of: (a) generating a reference current through a first transistor; (b) coupling said first transistor to a first input of an amplifier; (c) adjusting a current flowing through a second transistor by applying an output of said amplifier to said second transistor; (d) mirroring said current flowing through said second transistor with a current mirror circuit; (e) coupling said current mirror circuit to a third transistor; and (f) coupling said third transistors to a second input of said amplifier.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |