Abstract A voltage generator circuit includes a first feedback transistor coupled between a supply voltage source and a first bias node, and a gate coupled to an output node. A first bias MOS transistor of a first conductivity type has a first signal terminal and a back-bias terminal coupled to the first bias node, and a gate and second signal terminal coupled to a tracking node. A second bias MOS transistor of a second conductivity type has a gate and a first signal terminal coupled to the tracking node, and a second signal terminal coupled to a second bias node. A second feedback transistor is coupled between the second bias node and a reference voltage source, and has a gate coupled to the output node. A first drive MOS transistor has a first signal terminal coupled to the supply voltage source, a gate coupled to the first bias node, and a second signal terminal coupled to the output node. A second drive MOS transistor has a first signal terminal coupled to the output node, a second signal terminal coupled to the reference voltage source, and a gate coupled to the second bias node.
A method for generating a voltage on an output node in a memory device, the voltage being generated in response to first and second bias voltages developed on first and second bias nodes, respectively, by two diode-coupled MOS transistors connected in series between the first and second bias nodes, one diode-coupled transistor receiving its back-bias voltage from the first bias node and the other diode-coupled transistor having its source coupled to the second bias node, the method comprising the steps of: applying a supply voltage to the memory device; driving the first bias voltage on the first bias node toward the supply voltage when the output voltage drops below a desired value; driving the output voltage toward the supply voltage in response to the first bias voltage; driving the second bias voltage on the second bias node toward a reference voltage when the output voltage rises above the desired value; and driving the output voltage toward the reference voltage in response to the second bias voltage.
Claim 2
Independent Claim
166 words
A method for generating a voltage on an output node in a memory device, the voltage being generated in response to first and second bias voltages developed on first and second bias nodes, respectively, by two diode-coupled MOS transistors connected in series between the first and second bias nodes, one diode-coupled transistor receiving its back-bias voltage from the first bias node and the other diode-coupled transistor having its source coupled to the second bias node, the method comprising the steps of: applying a supply voltage to the memory device; driving the first bias voltage on the first bias node toward the supply voltage when the output voltage drops below a desired value; driving the output voltage toward the supply voltage in response to the first bias voltage; driving the second bias voltage on the second bias node toward a reference voltage when the output voltage rises above the desired value; and driving the output voltage toward the reference voltage in response to the second bias voltage.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein the supply voltage is approximately equal to five volts and the reference voltage is approximately equal to zero volts.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the desired value of the output voltage equals approximately the supply voltage divided by two.