Patent US6025733A successfully refreshed from Google Patents.
US6025733A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Renesas Electronics Corp
•
Filing: 1998-02-03
•
Granted: 2000-02-15
•
Expires: 2018-02-03
Abstract
Abstract A semiconductor memory device includes two subcircuits each including a memory circuit, a semiconductor circuit, and a logical circuit. Connection pads are divided into only two parallel rows located along the outer periphery of the semiconductor memory device. Each of the pads may include a probe region against which a probe is pressed for testing the semiconductor memory circuit, and a wire region to which a wire is connected upon packaging.
Inventors
- 👤 Tuyoshi Saitoh
- 👤 Akira Kitaguchi
- 👤 Masaaki Matsuo
- 👤 Makoto Hatakenaka
- 👤 Toshio Nakano
- 👤 Yuko Sudo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48; H; H10; H10W; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/90; H10W72/921; H10W72/926; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
166 words
A semiconductor memory device comprising: a semiconductor substrate; a semiconductor memory circuit including a first memory circuit and a second memory circuit used for replacing said first memory circuit when said first memory circuit fails to function properly; a semiconductor test circuit for testing said semiconductor memory circuit; a semiconductor circuit coupled to said semiconductor memory circuit and to said semiconductor test circuit; and a plurality of pads for contact by probes during testing of said semiconductor memory circuit and for connection to wires connected to lead terminals during packaging of said semiconductor memory device, said semiconductor memory circuit, said semiconductor test circuit, and said semiconductor circuit, said plurality of pads being located on said semiconductor substrate, and said plurality of pads being arranged in at least two rows, each row having a row direction parallel to a first side of an outer periphery of said semiconductor memory device, wherein none of said pads in different rows are aligned along directions perpendicular to the row direction.
Claim 2
Dependent Claim
166 words
A semiconductor memory device comprising: a semiconductor substrate; a semiconductor memory circuit including a first memory circuit and a second memory circuit used for replacing said first memory circuit when said first memory circuit fails to function properly; a semiconductor test circuit for testing said semiconductor memory circuit; a semiconductor circuit coupled to said semiconductor memory circuit and to said semiconductor test circuit; and a plurality of pads for contact by probes during testing of said semiconductor memory circuit and for connection to wires connected to lead terminals during packaging of said semiconductor memory device, said semiconductor memory circuit, said semiconductor test circuit, and said semiconductor circuit, said plurality of pads being located on said semiconductor substrate, and said plurality of pads being arranged in at least two rows, each row having a row direction parallel to a first side of an outer periphery of said semiconductor memory device, wherein none of said pads in different rows are aligned along directions perpendicular to the row direction.
Claim 3
Dependent Claim
35 words
The semiconductor memory device according to claim 1, wherein each of said pads comprises a probe region for contact by a probe during testing and a wire region for connection to a wire during packaging.
Claim 4
Dependent Claim
48 words
The semiconductor memory device according to claim 1, wherein each of said pads comprises a probe pad for contact by a probe during testing and a wire pad for connection to a wire during packaging, said probe pads and said wire pads being electrically connected to each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |