US5670890A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
Assignee: LSI Corp
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Filing: 1995-09-26
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Granted: 1997-09-23
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Expires: 2015-09-26
Abstract
Abstract An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.
Inventors
- 👤 Michael Colwell
- 👤 Rochit Rajsuman
- 👤 Ray Abrishami
- 👤 Zarir B. Sarkari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:35
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G01R31/3008
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
174 words
An integrated circuit having a normal mode of operation and a test mode of operations, comprising: logic means responsive to at least one of a plurality of input signal lines, each signal line having an electrical potential associated therewith; switchable pull circuit means coupled to said plurality of input signal lines for helping input signals carried thereon to pull to a desired potential level during the normal mode of operation; quiescent power means coupled to said switchable pull circuit means to enable it to receive a voltage potential for helping to pull the input signals to said desired potential level during the normal mode of operation; and IDDQ test control means coupled to said switchable pull circuit means for causing it to switch between the normal mode of operation permitting input signals to be pulled to said desired potential level, and the test mode of operation permitting each signal line having an electrical potential associate therewith to float to said electrical potential without being pulled to said desired potential level for IDDQ testing purposes.
Claim 2
Dependent Claim
174 words
An integrated circuit having a normal mode of operation and a test mode of operations, comprising: logic means responsive to at least one of a plurality of input signal lines, each signal line having an electrical potential associated therewith; switchable pull circuit means coupled to said plurality of input signal lines for helping input signals carried thereon to pull to a desired potential level during the normal mode of operation; quiescent power means coupled to said switchable pull circuit means to enable it to receive a voltage potential for helping to pull the input signals to said desired potential level during the normal mode of operation; and IDDQ test control means coupled to said switchable pull circuit means for causing it to switch between the normal mode of operation permitting input signals to be pulled to said desired potential level, and the test mode of operation permitting each signal line having an electrical potential associate therewith to float to said electrical potential without being pulled to said desired potential level for IDDQ testing purposes.
Claim 3
Dependent Claim
82 words
An integrated circuit according to claim 1, wherein said switchable pull circuit means includes: a plurality of pull transistors connected between the input signal lines respectively and said quiescent power means; and wherein said IDDQ test control means includes: test signal generating means for generating an IDDQ test control signal that turns off the pull transistors during the test mode of operation; and an IDDQ test signal line that is connected to the test signal generating means and to the pull transistors.
Claim 4
Dependent Claim
32 words
An integrated circuit as in claim 2, in which: the pull transistors are spaced from each other within a periphery of the circuit; and the IDDQ test signal line forms a ring.
Claim 5
Dependent Claim
24 words
An integrated circuit as in claim 3, further comprising logic devices that are disposed within said ring and are connected to the signal lines.
Claim 6
Dependent Claim
24 words
An integrated circuit as in claim 3, further comprising signal ports that are disposed outside said ring and connected to the signal lines respectively.
Claim 7
Dependent Claim
23 words
An integrated circuit as in claim 3, further comprising a chain of boundary scan cells that are connected to the signal lines respectively.
Claim 8
Dependent Claim
32 words
An integrated circuit as in claim 6, in which the test signal generating means comprises one of the boundary scan cells which has an output connected to the IDDQ test signal line.
Claim 9
Dependent Claim
35 words
An integrated circuit as in claim 3, in which the test signal generating means comprises a boundary scan system including a test access port controller having an output connected to the IDDQ test signal line.
Claim 10
Dependent Claim
59 words
An integrated circuit as in claim 3, in which the test signal generating means comprises: a buffer having an input and an output, the output of the buffer being connected to the IDDQ test signal line; and a buffer pull transistor which is connected between the input of the buffer and an electrical potential, and is constantly turned on.
Claim 11
Dependent Claim
15 words
An integrated circuit as in claim 9, in which the buffer is an inverting buffer.
Claim 12
Dependent Claim
141 words
A microelectronic device, comprising: a signal line having an electrical potential associated therewith; a pull transistor connected to said signal line for helping an input signal carried thereon to pull from said electrical potential to a first desired operating potential level during a normal mode of operation; quiescent means coupled to said pull transistor to enable it to receive a voltage potential of a sufficient potential level to pull the input signal to said desired operating potential level during said normal mode of operation; and IDDQ test control means for turning on the pull transistor during said normal mode of operation to enable it to pull said input signal from said electrical potential to said desired operating potential level, and for turning off the pull transistor to permit said signal line to float to said electrical potential for IDDQ testing purposes.
Claim 13
Dependent Claim
141 words
A microelectronic device, comprising: a signal line having an electrical potential associated therewith; a pull transistor connected to said signal line for helping an input signal carried thereon to pull from said electrical potential to a first desired operating potential level during a normal mode of operation; quiescent means coupled to said pull transistor to enable it to receive a voltage potential of a sufficient potential level to pull the input signal to said desired operating potential level during said normal mode of operation; and IDDQ test control means for turning on the pull transistor during said normal mode of operation to enable it to pull said input signal from said electrical potential to said desired operating potential level, and for turning off the pull transistor to permit said signal line to float to said electrical potential for IDDQ testing purposes.
Claim 14
Dependent Claim
16 words
A microelectronic device as in claim 11, in which the pull transistor is a pull-up transistor.
Claim 15
Dependent Claim
16 words
A microelectronic device as in claim 11, in which the pull transistor is a pull-down transistor.
Claim 16
Dependent Claim
64 words
A microelectronic device as in claim 11, in which: the pull transistor is a pull-up transistor; the device further comprises a pull-down transistor connected between the signal line and a second electrical potential which is lower than the first electrical potential; and the IDDQ test control means turns on the pull-down transistor for normal operation, and turns off the pull-down transistor for IDDQ testing.
Claim 17
Dependent Claim
28 words
A microelectronic device as in claim 14, further comprising an invertor connected between the IDDQ test control means and one of the pull-up transistor and the pull-down transistor.
Claim 18
Dependent Claim
64 words
A microelectronic device as in claim 11, in which: the pull transistor is a field effect transistor having a source, drain, channel and gate; the pull transistor is connected such that current flows between the signal line and the first electrical potential through the source, drain and channel thereof; and the IDDQ test control means is connected to the gate of the pull transistor.
Claim 19
Dependent Claim
59 words
A microelectronic device as in claim 11, in which the IDDQ test control means comprises: a buffer having an input for receiving an IDDQ test control signal and an output connected to the pull transistor; and a buffer pull transistor which is connected between the input of the buffer and a second electrical potential and is constantly turned on.
Claim 20
Dependent Claim
15 words
A microelectronic device as in claim 17, in which the buffer is an inverting buffer.
Claim 21
Dependent Claim
72 words
A microelectronic device as in claim 11, in which: the IDDQ test control means comprises: a signal port; a boundary scan cell connected between the signal port and the signal line; and a test access port controller for controlling the boundary scan cell to selectively connect the signal port to the signal line; and the test access port controller comprises means for applying an IDDQ test control signal to the pull transistor.
Claim 22
Dependent Claim
39 words
A microelectronic device as in claim 11, in which the IDDQ test control means comprises a boundary scan test system including a boundary scan cell which is connected to apply an IDDQ test control signal to the pull transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |