Patent US6025705A successfully refreshed from Google Patents.
US6025705A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DC-to-DC converter
Assignee: Intel Corp
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Filing: 1997-12-24
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Granted: 2000-02-15
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Expires: 2017-12-24
Abstract
Abstract Briefly, in accordance with one embodiment of the invention, a circuit includes a DC-to-DC converter. The DC-to-DC converter includes a high-side field effect transistor (FET) and FET driver. The gate of the high-side FET is AC coupled to the FET driver. The gate-to-source electrical path of the high-side FET is coupled to be driven by a substantially fixed voltage during circuit operation.
Inventors
- 👤 Donald J. Nguyen
- 👤 Geron Mark Johnston
- 👤 Robert D. Wickersham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:46
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; H02M3/158; H02M3/1588; G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
48 words
A circuit comprising: a DC-to-DC converter including a high-side FET and FET driver; the gate of said high-side FET being AC coupled to said FET driver; the gate-to-source electrical path of said high-side FET being coupled to be driven by a substantially fixed positive voltage during circuit operation.
Claim 2
Dependent Claim
48 words
A circuit comprising: a DC-to-DC converter including a high-side FET and FET driver; the gate of said high-side FET being AC coupled to said FET driver; the gate-to-source electrical path of said high-side FET being coupled to be driven by a substantially fixed positive voltage during circuit operation.
Claim 3
Dependent Claim
56 words
The circuit of claim 1, wherein said DC-to-DC converter comprises a synchronous DC-to-DC converter including a low-side FET and FET driver; the gate of said low-side FET being AC coupled to said low-side FET driver; the gate-to-source electrical path of said low-side FET being coupled to be driven by a substantially fixed voltage during circuit operation.
Claim 4
Dependent Claim
14 words
The circuit of claim 2, wherein said FETs are AC coupled via a capacitor.
Claim 5
Dependent Claim
47 words
The circuit of claim 3, wherein said gate-to-source electrical paths each comprise a diode; said diode being coupled so that an AC signal applied to said gate via said capacitor is referenced at one diode voltage drop below the voltage at the source of said high-side FET.
Claim 6
Dependent Claim
17 words
The circuit of claim 4, wherein said diode is coupled in parallel with a resistive circuit element.
Claim 7
Dependent Claim
74 words
A circuit comprising: a DC-to-DC converter including a high-side FET and FET driver; the gate of said high-side FET being AC coupled to said FET driver; the gate-to-source electrical path of said hiqh-side FET being coupled to be driven by a substantially fixed voltage during circuit operation, wherein said gate-to-source electrical path comprises a diode coupled in parallel with a resistive circuit element, wherein a zener diode is coupled in series with said diode.
Claim 8
Dependent Claim
74 words
A circuit comprising: a DC-to-DC converter including a high-side FET and FET driver; the gate of said high-side FET being AC coupled to said FET driver; the gate-to-source electrical path of said hiqh-side FET being coupled to be driven by a substantially fixed voltage during circuit operation, wherein said gate-to-source electrical path comprises a diode coupled in parallel with a resistive circuit element, wherein a zener diode is coupled in series with said diode.
Claim 9
Dependent Claim
14 words
The circuit of claim 1, wherein said FET is AC coupled via a capacitor.
Claim 10
Dependent Claim
46 words
The circuit of claim 7, wherein said gate-to-source electrical path comprises a diode, said diode being coupled so that an AC signal applied to said gate via said capacitor is referenced at one diode voltage drop below the voltage at the source of said high-side FET.
Claim 11
Dependent Claim
16 words
The circuit of claim 8, wherein said diode is coupled in parallel with a resistive element.
Claim 12
Independent Claim
59 words
A method of driving a high-side field effect transistor (FET) in a DC-to-DC converter comprising: applying an alternating voltage signal with substantially no DC component to the gate of said FET, the gate of said FET being referenced to a voltage signal that is a substantially fixed positive voltage drop from the voltage at the source of said FET.
Claim 13
Independent Claim
59 words
A method of driving a high-side field effect transistor (FET) in a DC-to-DC converter comprising: applying an alternating voltage signal with substantially no DC component to the gate of said FET, the gate of said FET being referenced to a voltage signal that is a substantially fixed positive voltage drop from the voltage at the source of said FET.
Claim 14
Dependent Claim
22 words
The method of claim 10, wherein the alternating voltage signal is applied to the gate by an FET driver via a capacitor.
Claim 15
Dependent Claim
16 words
The method of claim 11, wherein the substantially fixed voltage drop comprises one diode voltage drop.
Claim 16
Dependent Claim
63 words
The method of claim 10, wherein said DC-to-DC converter includes a low-side FET; and further comprising: applying an alternating voltage signal with substantially no DC component to the gate of said low-side FET, the gate of said low-side FET being referenced to a voltage signal level that is a substantially fixed voltage drop from the voltage at the source of said low-side FET.
Claim 17
Dependent Claim
26 words
The method of claim 13, wherein the substantially fixed voltage drop from the voltage at the source of said low-side FET comprises one diode voltage drop.
Claim 18
Dependent Claim
28 words
The method of claim 13, where the substantially fixed voltage drop from the voltage at the source of said low-side FET comprises more than one diode voltage drop.
Claim 19
Dependent Claim
24 words
The method of claim 13, and further comprising: modulating said alternating voltage signals to produce the desired output voltage signal of said DC-to-DC converter.
Claim 20
Dependent Claim
26 words
The method of claim 16, wherein said alternating voltage signals are modulated using feedback control based, at least in part, on the output voltage signal produced.
Claim 21
Dependent Claim
66 words
A circuit comprising: a DC-to-DC converter including a high-side FET and FET driver; the gate of said high-side FET being AC coupled to said FET driver; the gate-to-source electrical path of said high-side FET being coupled to be driven by a substantially fixed voltage during circuit operation, wherein said high-side FET and said FET driver are coupled so as to employ separate power sources in operation.
Claim 22
Dependent Claim
66 words
A circuit comprising: a DC-to-DC converter including a high-side FET and FET driver; the gate of said high-side FET being AC coupled to said FET driver; the gate-to-source electrical path of said high-side FET being coupled to be driven by a substantially fixed voltage during circuit operation, wherein said high-side FET and said FET driver are coupled so as to employ separate power sources in operation.
Claim 23
Dependent Claim
29 words
The circuit of claim 18, wherein said high-side FET and said FET driver are coupled so as to employ separate power sources that apply different respective voltages in operation.
Claim 24
Dependent Claim
32 words
The circuit of claim 19, wherein said high-side FET and said FET driver are coupled so that in operation said high-side FET employs a higher voltage power source than said FET driver.
Claim 25
Dependent Claim
36 words
The circuit of claim 1, wherein said high-side FET comprises a P-channel FET and said DC-to-DC converter includes an inductor coupled so that said inductor provides a filtered DC voltage output signal at its output port.
References Cited (Backward Citations)
US4578630A
Cited
US4745537A
Cited
US5289360A
Cited
US5282124A
Cited
US5744943A
Cited
US5602724A
Cited
US5705919A
Cited
US5811962A
Cited
US5847554A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-14 | 2003-08-16 | 2004-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-14 | 2007-08-16 | 2008-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-14 | 2011-08-16 | 2012-02-15 | $7700.00 | Window Closed / Lapsed |