US6025255A
Expired / Lapsed
US
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Two-step etching process for forming self-aligned contacts
Assignee: Vanguard International Semiconductor Corp
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Filing: 1998-06-25
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Granted: 2000-02-15
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Expires: 2018-06-25
Abstract
Abstract The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts. The invention describes a two step etching process whereby the contact opening is initially etched at high selectivity, and then, as the contact channel narrows, the polymer formation rate is reduced to prevent polymer pinch off and assure clearance of insulator in the contact area. The method performs both etch steps and the polymer and photoresist removal successively within the same RIE tool.
Inventors
- 👤 Bi-Ling Chen
- 👤 Erik S. Jerry
- 👤 Daniel Hao-Tien Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
253 words
A method for forming a self-aligned contact to a semiconductor element adjacent to a gate electrode of a MOSFET comprising: (a) providing a silicon wafer having a vertical walled gate stack with an insulative cap, a sidewall structure, and an active semiconductor element within the surface of said silicon wafer adjacent to said sidewall; (b) depositing an insulative layer over said silicon wafer; (c) planarizing said insulative layer; (d) depositing a photoresist layer over said insulative layer; (e) patterning said photoresist layer to define a contact opening; (f) etching said insulative layer by RIE for a first time period in a first flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a first rf power density whereby a polymer is formed over exposed silicon nitride surfaces; (g) etching said insulative layer by RIE for a second time period in a second flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a second rf power density wherein the second rf power density is higher than the first rf power density; (h) removing residual polymer by flowing an oxidizing gas in a carrier gas in three stages with successively increasing oxygen flow rates and successively decreasing rf power densities, whereby residual polymer is cleared from said contact opening and said active semiconductor element is exposed; (i) removing said photoresist layer by ashing; and (j) depositing a conductive material into said contact opening, thereby forming a self-aligned contact.
Claim 2
Independent Claim
253 words
A method for forming a self-aligned contact to a semiconductor element adjacent to a gate electrode of a MOSFET comprising: (a) providing a silicon wafer having a vertical walled gate stack with an insulative cap, a sidewall structure, and an active semiconductor element within the surface of said silicon wafer adjacent to said sidewall; (b) depositing an insulative layer over said silicon wafer; (c) planarizing said insulative layer; (d) depositing a photoresist layer over said insulative layer; (e) patterning said photoresist layer to define a contact opening; (f) etching said insulative layer by RIE for a first time period in a first flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a first rf power density whereby a polymer is formed over exposed silicon nitride surfaces; (g) etching said insulative layer by RIE for a second time period in a second flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a second rf power density wherein the second rf power density is higher than the first rf power density; (h) removing residual polymer by flowing an oxidizing gas in a carrier gas in three stages with successively increasing oxygen flow rates and successively decreasing rf power densities, whereby residual polymer is cleared from said contact opening and said active semiconductor element is exposed; (i) removing said photoresist layer by ashing; and (j) depositing a conductive material into said contact opening, thereby forming a self-aligned contact.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein said insulative layer is selected from the group consisting of silicon oxide, a phosphosilicate glass, and a borophosphosilicate glass.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein said insulative cap and said insulative sidewall structure is silicon nitride.
Claim 5
Dependent Claim
22 words
The method of claim 1 wherein the width of said contact opening at its base is between about 0.1 and 0.4 microns.
Claim 6
Dependent Claim
20 words
The method of claim 1 wherein the height of said vertical walled stack is between about 230 and 500 nm.
Claim 7
Dependent Claim
22 words
The method of claim 1 wherein the thickness of said sidewall structure at it's base is between about 50 and 100 nm.
Claim 8
Dependent Claim
19 words
The method of claim 1 wherein the thickness of said insulative cap is between about 150 and 250 nm.
Claim 9
Dependent Claim
40 words
The method of claim 1 wherein said first flow comprises C 4 F 8 at a flow rate of between about 10 and 15 SCCM and CH 3 F at a flow rate of between about 8 and 15 SCCM.
Claim 10
Dependent Claim
59 words
The method of claim 1 wherein said second flow comprises C 4 F 8 at flow rate of about 10 percent of the flow rate of C 4 F 8 in said first flow and CH 3 F at about a flow rate of about 30 percent of the flow rate of CH 3 F in said first flow.
Claim 11
Dependent Claim
17 words
The method of claim 1 wherein said first rf power density is 4.6 Watts/cm 2 or thereabout.
Claim 12
Dependent Claim
17 words
The method of claim 1 wherein said second rf power density is 5.2 Watts/cm 2 or thereabout.
Claim 13
Dependent Claim
29 words
The method of claim 1 wherein the flow rate of said argon carrier gas is adjusted to maintain a total chamber pressure of between about 2 and 10 mTorr.
Claim 14
Dependent Claim
38 words
The method of claim 1 wherein said successively increasing oxygen flow rates are 25, 35, and 100 SCCM or thereabout respectively and said successively decreasing rf power densities are 0.46, 0.39, and 0.31 Watts/cm 2 or thereabout respectively.
Claim 15
Independent Claim
348 words
A method for forming a DRAM cell structure having a self-aligned bitline contact to a semiconductive element between two adjacent wordlines comprising: (a) providing a silicon wafer having a gate oxide layer subjacent to a conductive layer; (b) depositing a silicon oxide layer over said conductive layer; (c) depositing a first silicon nitride layer, over said silicon oxide layer; (d) depositing and patterning a first photoresist layer to define a plurality of wordlines; (e) anisotropically etching said first silicon nitride layer, said silicon oxide layer, and said conductive layer thereby forming wordlines; (f) implanting a first dose of impurity atoms; (g) removing said first photoresist layer; (h) depositing a second silicon nitride layer; (i) anisotropically etching said second silicon nitride layer thereby forming silicon nitride sidewalls adjacent to said wordlines; (j) implanting a second dose of impurity atoms thereby forming a semiconductive element; (k) depositing an insulative layer over said silicon wafer; (l) planarizing said insulative layer; (m) depositing a second photoresist layer over said insulative layer; (n) patterning said second photoresist layer to define a bitline contact openings between adjacent wordlines; (o) etching said insulative layer by RIE for a first time period in a first flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a first rf power density whereby a polymer is formed over exposed silicon nitride surfaces; (p) etching said insulative layer by RIE for a second time period in a second flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a second rf power density thereby forming bitline contact openings wherein the second rf power density is higher than the first rf power density; (q) removing residual polymer by flowing an oxidizing gas in a carrier gas in three stages with successively increasing oxygen flow rates and successively decreasing rf power densities; (r) removing said photoresist layer by ashing; (s) depositing conductive material into said bitline contact openings, thereby forming bitline contacts; (t) forming a bitline over said bitline contact; and (u) forming storage capacitors.
Claim 16
Independent Claim
348 words
A method for forming a DRAM cell structure having a self-aligned bitline contact to a semiconductive element between two adjacent wordlines comprising: (a) providing a silicon wafer having a gate oxide layer subjacent to a conductive layer; (b) depositing a silicon oxide layer over said conductive layer; (c) depositing a first silicon nitride layer, over said silicon oxide layer; (d) depositing and patterning a first photoresist layer to define a plurality of wordlines; (e) anisotropically etching said first silicon nitride layer, said silicon oxide layer, and said conductive layer thereby forming wordlines; (f) implanting a first dose of impurity atoms; (g) removing said first photoresist layer; (h) depositing a second silicon nitride layer; (i) anisotropically etching said second silicon nitride layer thereby forming silicon nitride sidewalls adjacent to said wordlines; (j) implanting a second dose of impurity atoms thereby forming a semiconductive element; (k) depositing an insulative layer over said silicon wafer; (l) planarizing said insulative layer; (m) depositing a second photoresist layer over said insulative layer; (n) patterning said second photoresist layer to define a bitline contact openings between adjacent wordlines; (o) etching said insulative layer by RIE for a first time period in a first flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a first rf power density whereby a polymer is formed over exposed silicon nitride surfaces; (p) etching said insulative layer by RIE for a second time period in a second flow of fluorocyclobutane (C 4 F 8 ) and CH 3 F in an argon carrier gas at a second rf power density thereby forming bitline contact openings wherein the second rf power density is higher than the first rf power density; (q) removing residual polymer by flowing an oxidizing gas in a carrier gas in three stages with successively increasing oxygen flow rates and successively decreasing rf power densities; (r) removing said photoresist layer by ashing; (s) depositing conductive material into said bitline contact openings, thereby forming bitline contacts; (t) forming a bitline over said bitline contact; and (u) forming storage capacitors.
Claim 17
Dependent Claim
25 words
The method of claim 14 wherein said insulative layer is selected from the group consisting of silicon oxide, a phosphosilicate glass, and a borophosphosilicate glass.
Claim 18
Dependent Claim
20 words
The method of claim 14 wherein the width of said bitline contact openings is between about 0.1 and 0.4 microns.
Claim 19
Dependent Claim
20 words
The method of claim 14 wherein the thickness of said silicon nitride sidewalls is between about 50 and 100 nm.
Claim 20
Dependent Claim
18 words
The method of claim 14 wherein the distance between adjacent wordlines is between about 0.18 and 0.35 microns.
Claim 21
Dependent Claim
40 words
The method of claim 14 wherein said first flow comprises C 4 F 8 at a flow rate of between about 10 and 15 SCCM and CH 3 F at a flow rate of between about 8 and 15 SCCM.
Claim 22
Dependent Claim
59 words
The method of claim 14 wherein said second flow comprises C 4 F 8 at flow rate of about 10 percent of the flow rate of C 4 F 8 in said first flow and CH 3 F at about a flow rate of about 30 percent of the flow rate of CH 3 F in said first flow.
Claim 23
Dependent Claim
17 words
The method of claim 14 wherein said first rf power density is 4.6 Watts/cm 2 or thereabout.
Claim 24
Dependent Claim
17 words
The method of claim 14 wherein said second rf power density is 5.2 Watts/cm 2 or thereabout.
Claim 25
Dependent Claim
29 words
The method of claim 14 wherein the flow rate of said argon carrier gas is adjusted to maintain a total chamber pressure of between about 2 and 10 mTorr.
Claim 26
Dependent Claim
38 words
The method of claim 14 wherein said successively increasing oxygen flow rates are 25, 35, and 100 SCCM or thereabout respectively and said successively decreasing rf power densities are 0.46, 0.39, and 0.31 Watts/cm 2 or thereabout respectively.
Claim 27
Dependent Claim
11 words
The method of claim 14 wherein said conductive material is tungsten.
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