CMOS integrated circuit device and inspection method thereof

Claim 1

A CMOS integrated circuit device comprising: a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to said n-type substrate or said n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed.

Claim 10

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed, comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.

Claim 11

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed, comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.

Claim 12

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; and a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.

Claim 13

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; and a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.

Claim 14

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.

Claim 15

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.

Claim 16

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.

Claim 17

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.

Claim 18

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.

Claim 19

A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.