US5838047A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS substrate biasing for threshold voltage control
Assignee: Renesas Electronics Corp
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Filing: 1996-06-14
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Granted: 1998-11-17
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Expires: 2016-06-14
Abstract
Abstract A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.
Inventors
- 👤 Tadaaki Yamauchi
- 👤 Kazutami Arimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:43
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; Y; Y10; Y10S; Y10S257/00; Y10S257/901
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
155 words
A semiconductor device comprising: a P channel MOS transistor having a standby state and an active state, an N channel MOS transistor having a standby state and an active state, first potential supply means for supplying to a substrate of said P channel MOS transistor a first potential equal to or higher than a potential of a source electrode of said P channel MOS transistor when said P channel MOS transistor attains a standby state, second potential supply means for supplying to a substrate of said N channel MOS transistor a second potential equal to or lower than a potential of a source electrode of said N channel MOS transistor when said N channel MOS transistor attains a standby state, and short circuit means for short-circuiting the substrate of said P channel MOS transistor and the substrate of said N channel MOS transistor when said P and N channel MOS transistors attain an active state.
Claim 2
Dependent Claim
155 words
A semiconductor device comprising: a P channel MOS transistor having a standby state and an active state, an N channel MOS transistor having a standby state and an active state, first potential supply means for supplying to a substrate of said P channel MOS transistor a first potential equal to or higher than a potential of a source electrode of said P channel MOS transistor when said P channel MOS transistor attains a standby state, second potential supply means for supplying to a substrate of said N channel MOS transistor a second potential equal to or lower than a potential of a source electrode of said N channel MOS transistor when said N channel MOS transistor attains a standby state, and short circuit means for short-circuiting the substrate of said P channel MOS transistor and the substrate of said N channel MOS transistor when said P and N channel MOS transistors attain an active state.
Claim 3
Dependent Claim
54 words
The semiconductor device according to claim 1, further comprising intermediate potential supply means for supplying a potential intermediate between said first potential and said second potential to the substrate of said P channel MOS transistor and the substrate of said N channel MOS transistor at the time of short-circuiting by said short circuit means.
Claim 4
Dependent Claim
39 words
The semiconductor device according to claim 1, further comprising parasitic capacitance adjusting means for adjusting a parasitic capacitance of the substrate of said P channel MOS transistor to equal that of the substrate of said N channel MOS transistor.
Claim 5
Dependent Claim
34 words
The semiconductor device according to claim 3, wherein said parasitic capacitance adjusting means comprises a capacitor connected to the substrate of one of said P channel MOS transistor and said N channel MOS transistor.
Claim 6
Dependent Claim
37 words
The semiconductor device according to claim 3, wherein said parasitic capacitance adjusting means comprises a dummy transistor always inactivated and connected in parallel to one of said P channel MOS transistor and said N channel MOS transistor.
Claim 7
Dependent Claim
23 words
The semiconductor device according to claim 1, further comprising an SOI substrate on which said P and N channel MOS transistors are formed.
Claim 8
Dependent Claim
165 words
A semiconductor device comprising: a P channel MOS transistor having a standby state and an active state, an N channel MOS transistor having a standby state and an active state, first potential supply means for supplying to a substrate of said P channel MOS transistor a first potential equal to or higher than a potential of a source electrode of said P channel MOS transistor when said P channel MOS transistor attains a standby state, second potential supply means for supplying to a substrate of said N channel MOS transistor a second potential equal to or lower than a potential of a source electrode of said N channel MOS transistor when said N channel MOS transistor attains a standby state, and intermediate potential supply means for supplying a potential intermediate between said first potential and said second potential to the substrates of said P channel MOS transistor and said N channel MOS transistor when said P and N channel MOS transistors attain an active state.
Claim 9
Dependent Claim
165 words
A semiconductor device comprising: a P channel MOS transistor having a standby state and an active state, an N channel MOS transistor having a standby state and an active state, first potential supply means for supplying to a substrate of said P channel MOS transistor a first potential equal to or higher than a potential of a source electrode of said P channel MOS transistor when said P channel MOS transistor attains a standby state, second potential supply means for supplying to a substrate of said N channel MOS transistor a second potential equal to or lower than a potential of a source electrode of said N channel MOS transistor when said N channel MOS transistor attains a standby state, and intermediate potential supply means for supplying a potential intermediate between said first potential and said second potential to the substrates of said P channel MOS transistor and said N channel MOS transistor when said P and N channel MOS transistors attain an active state.
Claim 10
Dependent Claim
23 words
The semiconductor device according to claim 7, further comprising an SOI substrate on which said P and N channel MOS transistors are formed.
Claim 11
Dependent Claim
180 words
A semiconductor device having a standby state and an active state, comprising: a first P type well, a first N channel MOS transistor formed on said first P type well, a first N type well, a first P channel MOS transistor formed on said first N channel well, a second P type well, a second N type MOS transistor formed on said second P type well, a second N type well, a second P channel MOS transistor formed on said second N type well, precharge means for precharging said first and second P type wells to a level of a ground potential and said first and second N type wells to a level of a power supply potential in said standby state, first short circuit means for short-circuiting said first and second P type wells and said first and second N type wells in said active state, and second short circuit means for short-circuiting said first P type well and said first N type well after precharging by said precharge means and before short-circuiting by said first short circuit means.
Claim 12
Dependent Claim
180 words
A semiconductor device having a standby state and an active state, comprising: a first P type well, a first N channel MOS transistor formed on said first P type well, a first N type well, a first P channel MOS transistor formed on said first N channel well, a second P type well, a second N type MOS transistor formed on said second P type well, a second N type well, a second P channel MOS transistor formed on said second N type well, precharge means for precharging said first and second P type wells to a level of a ground potential and said first and second N type wells to a level of a power supply potential in said standby state, first short circuit means for short-circuiting said first and second P type wells and said first and second N type wells in said active state, and second short circuit means for short-circuiting said first P type well and said first N type well after precharging by said precharge means and before short-circuiting by said first short circuit means.
Claim 13
Dependent Claim
332 words
A semiconductor device comprising: a first P channel MOS transistor turned on/off in response to an input signal, a second P channel MOS transistor turned on/off in response to an input signal, a first N channel MOS transistor turned on/off in response to an input signal, a second N channel MOS transistor turned on/off in response to an input signal, first potential supply means for supplying to a substrate of said first P channel MOS transistor a first potential equal to or higher than a potential of a source electrode of said first P channel MOS transistor when said first P channel MOS transistor is turned off, second potential supply means for supplying to a substrate of said second P channel MOS transistor a second potential equal to or higher than a potential of a source electrode of said second P channel MOS transistor when said second P channel MOS transistor is turned off, third potential supply means for supplying to a substrate of said first N channel MOS transistor a third potential equal to or lower than a potential of a source electrode of said first N channel MOS transistor when said first N channel MOS transistor is turned off, fourth potential supply means for supplying to a substrate of said second N channel MOS transistor a fourth potential equal to or lower than a potential of a source electrode of said second N channel MOS transistor when said second N channel MOS transistor is turned off, first short circuit means for short-circuiting the substrate of said second P channel MOS transistor and the substrate of said first N channel MOS transistor when said second P channel MOS transistor and said first N channel MOS transistor are turned on, and second short-circuit means for short-circuiting the substrate of said first P channel MOS transistor and the substrate of said second N channel MOS transistor when said first P channel MOS transistor and said second N channel MOS transistor are turned on.
Claim 14
Dependent Claim
332 words
A semiconductor device comprising: a first P channel MOS transistor turned on/off in response to an input signal, a second P channel MOS transistor turned on/off in response to an input signal, a first N channel MOS transistor turned on/off in response to an input signal, a second N channel MOS transistor turned on/off in response to an input signal, first potential supply means for supplying to a substrate of said first P channel MOS transistor a first potential equal to or higher than a potential of a source electrode of said first P channel MOS transistor when said first P channel MOS transistor is turned off, second potential supply means for supplying to a substrate of said second P channel MOS transistor a second potential equal to or higher than a potential of a source electrode of said second P channel MOS transistor when said second P channel MOS transistor is turned off, third potential supply means for supplying to a substrate of said first N channel MOS transistor a third potential equal to or lower than a potential of a source electrode of said first N channel MOS transistor when said first N channel MOS transistor is turned off, fourth potential supply means for supplying to a substrate of said second N channel MOS transistor a fourth potential equal to or lower than a potential of a source electrode of said second N channel MOS transistor when said second N channel MOS transistor is turned off, first short circuit means for short-circuiting the substrate of said second P channel MOS transistor and the substrate of said first N channel MOS transistor when said second P channel MOS transistor and said first N channel MOS transistor are turned on, and second short-circuit means for short-circuiting the substrate of said first P channel MOS transistor and the substrate of said second N channel MOS transistor when said first P channel MOS transistor and said second N channel MOS transistor are turned on.
Claim 15
Dependent Claim
89 words
The semiconductor device according to claim 10, further comprising: first intermediate potential supply means for supplying to the substrate of said second P channel MOS transistor and to the substrate of said first N channel MOS transistor a potential intermediate between said second potential and said third potential at the time of short-circuiting by said first short circuit means, and second intermediate potential supply means for supplying a potential intermediate between said first potential and said fourth potential at the time of short-circuiting by said second short circuit means.
Claim 16
Dependent Claim
80 words
The semiconductor device according to claim 10, further comprising: first parasitic capacitance adjusting means for adjusting a parasitic capacitance of the substrate of said first P channel MOS transistor to equal a parasitic capacitance of the substrate of said second N channel MOS transistor, and second parasitic capacitance adjusting means for adjusting a parasitic capacitance of the substrate of said second P channel MOS transistor to equal a parasitic capacitance of the substrate of said first N channel MOS transistor.
Claim 17
Dependent Claim
33 words
The semiconductor device according to claim 10, further comprising an SOI substrate on which said first P and N channel MOS transistors and said second P and N channel MOS transistors are formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |