US6023186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS integrated circuit device and inspection method thereof
Assignee: Toshiba Corp
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Filing: 1998-07-24
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Granted: 2000-02-08
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Expires: 2018-07-24
Abstract
Abstract A CMOS integrated circuit device enabling accurate inspection of its static power source current includes: a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of the p-channel MOS transistor; a second pad connected to the source of the n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well having formed the p-channel MOS transistor; an n-type diffused region formed in the p-type substrate or p-well having formed the n-channel MOS transistor; a third pad connected through the p-type diffused region to the n-type substrate or n-well having formed the p-channel MOS transistor; and a fourth pad connected through the n-type diffused region to the p-type substrate or p-well having formed the n-channel MOS transistor.
Inventors
- 👤 Tadahiro Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:05
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
128 words
A CMOS integrated circuit device comprising: a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to said n-type substrate or said n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed.
Claim 2
Dependent Claim
128 words
A CMOS integrated circuit device comprising: a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to said n-type substrate or said n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed.
Claim 3
Dependent Claim
60 words
The CMOS integrated circuit device according to claim 1 further comprising: a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; and a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad.
Claim 4
Dependent Claim
67 words
The CMOS integrated circuit device according to claim 1 wherein said first pad is connected to be applied with a first power source potential, said second pad being connected to be applied with a second power source potential, said third pad being connected to be applied with a third power source potential, and said fourth pad being connected to be applied with a fourth power source potential.
Claim 5
Dependent Claim
53 words
The CMOS integrated circuit device according to claim 1 further comprising a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor.
Claim 6
Dependent Claim
66 words
The CMOS integrated circuit device according to claim 2 wherein said pad is connected to be applied with a first power source potential, said second pad being connected to be applied with a second power source potential, said third pad being connected to be applied with a third power source potential, and said fourth pad being connected to be applied with a fourth power source potential.
Claim 7
Dependent Claim
53 words
The CMOS integrated circuit device according to claim 2 further comprising a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor.
Claim 8
Dependent Claim
121 words
A CMOS integrated circuit device comprising: a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a third pad connected to an n-type substrate or n-well in which said p-channel MOS transistor is formed; a fourth pad connected to a p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor.
Claim 9
Dependent Claim
121 words
A CMOS integrated circuit device comprising: a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a third pad connected to an n-type substrate or n-well in which said p-channel MOS transistor is formed; a fourth pad connected to a p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor.
Claim 10
Independent Claim
219 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed, comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.
Claim 11
Independent Claim
219 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; and a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed, comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.
Claim 12
Independent Claim
267 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; and a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.
Claim 13
Independent Claim
267 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; and a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by applying a first power source potential to said first pad, applying a second power source potential lower than said first source power potential to said second pad, applying a potential higher than said first power source potential to said third pad, and applying a potential lower than said second power source potential to said fourth pad.
Claim 14
Independent Claim
277 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.
Claim 15
Independent Claim
277 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.
Claim 16
Independent Claim
325 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.
Claim 17
Independent Claim
325 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well in which said p-channel MOS transistor is formed; an n-type diffused region formed in a p-type substrate or p-well in which said n-channel MOS transistor is formed; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; a second p-type diffused region formed in said n-type substrate or n-well having formed said p-channel MOS transistor and connected to said fourth pad; a second n-type diffused region formed in said p-type substrate or p-well having formed said n-channel MOS transistor and connected to said third pad; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.
Claim 18
Independent Claim
239 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.
Claim 19
Independent Claim
239 words
A method for inspecting a CMOS integrated circuit device having a CMOS circuit including a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of said p-channel transistor; a second pad connected to the source of said n-channel MOS transistor; a third pad connected through said p-type diffused region to an n-type substrate or an n-well in which said p-channel MOS transistor is formed; a fourth pad connected through said n-type diffused region to said p-type substrate or p-well in which said n-channel MOS transistor is formed; and a control circuit activated by an enable control signal to elevate the potential of said n-type substrate or n-well having formed said p-channel MOS transistor and to lower the potential of said p-type substrate or p-well having formed said n-channel MOS transistor; comprising: determining whether said CMOS integrated circuit device is acceptable or not with reference to a current flowing in said first or second pad under a condition made for inspection by first applying a first power source potential to said first pad and applying a second power source potential lower than said first source power potential to said second pad, next inactivating said control circuit in response to said enable control signal, and thereafter applying a potential higher than said first power source potential to said third pad and applying a potential lower than said second power source potential to said fourth pad.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-02-07 | 2003-08-09 | 2004-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-07 | 2007-08-09 | 2008-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-07 | 2011-08-09 | 2012-02-08 | $7700.00 | Window Closed / Lapsed |