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US6015753A
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Method of forming a self-aligned silicide
Assignee: United Microelectronics Corp
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Filing: 1998-06-24
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Granted: 2000-01-18
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Expires: 2018-06-24
Abstract
Abstract A method of forming a self-aligned salicide is provided. The invention twice performs selective epitaxial growth to form an amorphous silicon layer on gate electrodes and source/drain regions of a substrate after forming the gate electrodes and the source/drain regions. Then, a molybdenum impurity is doped to perform a silicidation process and to convert a metal deposited on the substrate into a salicide layer.
Inventors
- 👤 Tony Lin
- 👤 Hua-Chou Tseng
- 👤 Water Lur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
114 words
A method of forming a self-aligned silicide (salicide), the method comprising the steps of: providing a substrate on which is formed a field effect transistor comprising a gate, a source/drain region and a spacer formed on each sidewall of the gate; performing a first selective epitaxial process and a second selective epitaxial process to form an amorphous silicon layer on at least one selected from a group consisting of the gate, and the source/drain region; doping a molybdenum impurity into the amorphous silicon layer; forming a metal layer over the substrate; performing a thermal annealing process to convert the metal layer into a salicide layer; and removing an unreacted portion of the metal layer.
Claim 2
Independent Claim
114 words
A method of forming a self-aligned silicide (salicide), the method comprising the steps of: providing a substrate on which is formed a field effect transistor comprising a gate, a source/drain region and a spacer formed on each sidewall of the gate; performing a first selective epitaxial process and a second selective epitaxial process to form an amorphous silicon layer on at least one selected from a group consisting of the gate, and the source/drain region; doping a molybdenum impurity into the amorphous silicon layer; forming a metal layer over the substrate; performing a thermal annealing process to convert the metal layer into a salicide layer; and removing an unreacted portion of the metal layer.
Claim 3
Dependent Claim
50 words
The method according to claim 1, wherein the field effect transistor is formed on the substrate by steps comprising: forming the gate; performing a first ion implantation to form a lightly doped source/drain region; forming the spacer; and performing a second ion implantation to form a heavily doped source/drain region.
Claim 4
Dependent Claim
20 words
The method according to claim 1, wherein the first epitaxial process is performed at a temperature of about 200-450° C.
Claim 5
Dependent Claim
20 words
The method according to claim 1, wherein the second epitaxial process is performed at a temperature of about 450-900° C.
Claim 6
Dependent Claim
20 words
The method according to claim 1, wherein the thermal annealing process is performed at the temperature of about 600-800° C.
Claim 7
Dependent Claim
17 words
The method according to claim 5, wherein the thermal annealing process is a rapid thermal annealing process.
Claim 8
Dependent Claim
32 words
The method according to claim 1, wherein the step of removing the unreacted metal layer comprises etching in a solution of H 2 O 2 and NH 4 OH diluted in water.
Claim 9
Dependent Claim
12 words
The method according to claim 1, wherein the metal layer comprises titanium.
Claim 10
Dependent Claim
15 words
The method according to claim 1, wherein the metal layer comprises a refractory metallic material.
Claim 11
Dependent Claim
17 words
The method according to claim 1, wherein the thermal annealing process comprises a rapid thermal annealing process.
Claim 12
Dependent Claim
36 words
The method according to claim 1, wherein the first and the second selective epitaxial processes are respectively performed at a first temperature and a second temperature, where the first temperature is lower than the second temperature.
Claim 13
Dependent Claim
27 words
The method according to claim 1, wherein the thermal annealing process is performed at a temperature of about greater than 600° C. and less than 650° C.
Claim 14
Dependent Claim
27 words
The method according to claim 1, wherein the thermal annealing process is performed at a temperature of greater than 650° C. and about less than 900° C.
References Cited (Backward Citations)
US5824586A
Cited
US5902125A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-01-17 | 2003-07-19 | 2004-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-17 | 2007-07-19 | 2008-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-17 | 2011-07-19 | 2012-01-18 | $7700.00 | Window Closed / Lapsed |