US6014755A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of managing defects in flash disk memories
Assignee: Intel Corp
•
Filing: 1996-08-12
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Granted: 2000-01-11
•
Expires: 2016-08-12
Abstract
Abstract A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.
Inventors
- 👤 Steven E. Wells
- 👤 Eric J. Magnusson
- 👤 Robert N. Hasbun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:09
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/4401; G11C29/88; G11C2029/0409
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
89 words
A method for erase defect management in a memory comprising a plurality of memory arrays divided into individually erasable blocks of memory, said method comprising: a) executing an erase operation with a high erase voltage on a block of memory in a memory array; b) determining if an error occurred for the erase operation; c) determining if the high erase voltage is low; d) disabling write operations to the memory array, if the high erase voltage is low; and e) executing read operations to the memory array, if requested.
Claim 2
Independent Claim
89 words
A method for erase defect management in a memory comprising a plurality of memory arrays divided into individually erasable blocks of memory, said method comprising: a) executing an erase operation with a high erase voltage on a block of memory in a memory array; b) determining if an error occurred for the erase operation; c) determining if the high erase voltage is low; d) disabling write operations to the memory array, if the high erase voltage is low; and e) executing read operations to the memory array, if requested.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein the memory comprises flash electrically erasable programmable read only memory (EEPROM) memory cells.
Claim 4
Dependent Claim
19 words
The method of claim 1 wherein executing an erase operation further comprises: i) writing logical ones to the block.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein determining if an error occurred further comprises: i) comparing data stored in the block with logical ones.
Claim 6
Dependent Claim
23 words
The method of claim 4 wherein comparing data stored in the block with logical ones further comprises reading data stored in the block.
Claim 7
Dependent Claim
30 words
The method of claim 1 further comprising: f) marking a sector of the block being erased bad, if an erase error occurred and the high erase voltage is not low.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |