Prefetch management for DMA read transactions depending upon past history of actual transfer lengths

Claim 2

A process for providing data from a memory to a peripheral device in a data processing system in response to a direct memory access (DMA) read transaction request, the process comprising the steps of: (a) determining a memory page number from a starting memory address specified in the DMA read transaction request; (b) determining a prefetch length value given a memory page number, by accessing a page table that stores a prefetch length value for each of a plurality of pages in the memory; (c) prefetching data from a number of storage locations in the memory equal to the prefetch length value; (d) providing data to the peripheral device as retrieved from the memory until the DMA read transaction request terminates; (e) counting the actual total number of storage locations retrieved during the DMA read transaction; and (f) updating the prefetch length value for the page as a function of the actual number of locations transferred during the DMA read transaction.

Claim 3

A process as in claim 1 additionally comprising the steps of: (g) providing a plurality of storage locations for prefetch length values for each of a plurality of pages in the memory.

Claim 4

A process as in claim 2 additionally comprising the step of: (h) if step (d) of providing data to the peripheral device is terminated before all of the prefetched data from step (c) is provided to the peripheral device in step (d), storing the lesser actual number of locations read by the peripheral device as the prefetch length value.

Claim 5

A process as in claim 1 additionally comprising the step of: (i) assigning a memory page to each of several peripheral devices.

Claim 6

A process as in claim 1 additionally comprising the step of: (j) if the page table does not contain a prefetch length value for the page, prefetching a default number of storage locations.

Claim 7

A data processing system comprising: a central processing unit (CPU) for executing data processing program tasks; a memory, connected to the CPU, to store and retrieve data to be used by the data processing program tasks, the memory divided into a plurality of memory pages; at least one peripheral device connected to the data processing system via a peripheral device bus, such that the peripheral device issues direct memory access (DMA) read transaction requests over the peripheral device bus, the DMA read transaction requests specifying a memory address for a DMA read transaction, the memory address including a memory page field; a memory controller, connected to the peripheral device bus and the memory, such that in response to receiving a DMA read transaction request, the memory controller performs a DMA read transaction by reading data from the memory, causing the data to be provided to the peripheral device over the peripheral device bus; and a prefetch logic circuit, connected to the memory controller, such that, in response to the memory controller receiving a DMA read transaction request, a number of memory locations are prefetched from the memory prior to the data being provided to the peripheral device over the peripheral device bus, the prefetch logic circuit additionally comprising: a location counter, for counting an actual total number of memory locations read during a DMA read transaction; and a prefetch size register, connected to the counter and the memory controller, for storing the contents of the location counter as a prefetch length value, the prefetch size register also connected to control the number of memory locations prefetched during a DMA read transaction such that during a subsequent DMA read transaction request, the number of memory locations prefetched is equal to the actual total number of memory locations read during a prior DMA read transaction.

Claim 8

A data processing system comprising: a central processing unit (CPU) for executing data processing program tasks; a memory, connected to the CPU, to store and retrieve data to be used by the data processing program tasks, the memory divided into a plurality of memory pages; at least one peripheral device connected to the data processing system via a peripheral device bus, such that the peripheral device issues direct memory access (DMA) read transaction requests over the peripheral device bus, the DMA read transaction requests specifying a memory address for a DMA read transaction, the memory address including a memory page field; a memory controller, connected to the peripheral device bus and the memory, such that in response to receiving a DMA read transaction request, the memory controller performs a DMA read transaction by reading data from the memory, causing the data to be provided to the peripheral device over the peripheral device bus; and a prefetch logic circuit, connected to the memory controller, such that, in response to the memory controller receiving a DMA read transaction request, a number of memory locations are prefetched from the memory prior to the data being provided to the peripheral device over the peripheral device bus, the prefetch logic circuit additionally comprising: a location counter, for counting an actual total number of memory locations read during a DMA read transaction; and a prefetch size register, connected to the counter and the memory controller, for storing the contents of the location counter as a prefetch length value, the prefetch size register also connected to control the number of memory locations prefetched during a DMA read transaction such that during a subsequent DMA read transaction request, the number of memory locations prefetched is equal to the actual total number of memory locations read during a prior DMA read transaction.

Claim 9

A system as in claim 6 wherein the prefetch logic circuit is additionally connected to store a prefetch length value at the termination of a read transaction for a plurality of memory pages accessed thereby, and the prefetch length value depending upon a number of memory locations transferred during that read transaction for that particular page.

Claim 10

A system as in claim 6 wherein the memory is arranged for read access by cache line locations, and the prefetch length value specifies a number of cache lines.

Claim 11

A system as in claim 7 additionally comprising: a page table, connected to the prefetch logic circuit, the page table including a plurality of table entries, with a table entry for each of a number of pages in the memory, the page table storing a prefetch length value for each associated page indicating the amount of data transferred from the respective page on the last DMA read transaction with that page.

Claim 12

A system as in claim 9 wherein a page table entry is made for each of a plurality of data streams from a given peripheral device which initiated the DMA read transaction.