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US5581718A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for selecting instructions for simultaneous execution

Assignee: Intel Corp
•
Filing: 1994-07-15
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Granted: 1996-12-03
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Expires: 2014-07-15
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Abstract

Abstract A method and apparatus for selecting instructions from a sequence of undifferentiated bytes of instruction data is described. A first plurality of sequential bytes of instruction data is selected from the sequence of undifferentiated bytes of instruction data. A second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality is selected from the first plurality of sequential bytes of instruction data. A third plurality of sequential bytes of instruction data beginning at any selected byte in the second plurality is selected from the second plurality of sequential bytes of instruction data. The second plurality of sequential bytes is of sufficient length to provide instruction data for at least two clock cycles.

Inventors

  • 👤 Edward Grochowski

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 01:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3816; G06F9/30145; G06F9/30149

Claims Analysis

Total Claims: 28
Claim 1
Independent Claim 136 words
A circuit for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: means for providing a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; means for selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data by utilizing a pointer which indicates the last byte already processed; and means for selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data by utilizing said pointer which indicates the last byte already processed.
Claim 2
Dependent Claim 136 words
A circuit for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: means for providing a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; means for selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data by utilizing a pointer which indicates the last byte already processed; and means for selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data by utilizing said pointer which indicates the last byte already processed.
Claim 3
Independent Claim 130 words
A method for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: receiving a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data by utilizing a pointer which indicates the last byte already processed; and selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data by utilizing said pointer which indicates the last byte already processed.
Claim 4
Independent Claim 130 words
A method for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: receiving a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data by utilizing a pointer which indicates the last byte already processed; and selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data by utilizing said pointer which indicates the last byte already processed.
Claim 5
Dependent Claim 17 words
The method of claim 2 further comprising: generating said pointer to indicate the last byte already processed.
Claim 6
Dependent Claim 41 words
The method of claim 3 wherein generating said pointer to indicate the last byte already processed further comprises: deriving a length value for a first instruction processed; deriving a length value for a second instruction processed; and adding the length values.
Claim 7
Dependent Claim 41 words
The method of claim 3 wherein generating said pointer to indicate the last byte already processed further comprises: deriving a length value for each instruction of a plurality of instructions processed in a single clock cycle; and adding the length values.
Claim 8
Dependent Claim 35 words
The method of claim 2 wherein said third plurality of sequential bytes of instruction data is of sufficient size to include a plurality of maximum size instructions that can be processed in one clock cycle.
Claim 9
Dependent Claim 25 words
The method of claim 2 wherein said third plurality of sequential bytes of instruction data is of sufficient size to include two maximum size instructions.
Claim 10
Dependent Claim 35 words
The method of claim 2 wherein said second plurality of sequential bytes of instruction data is of sufficient size to include a plurality of maximum size instructions that can be processed in two clock cycles.
Claim 11
Dependent Claim 25 words
The method of claim 2 wherein said second plurality of sequential bytes of instruction data is of sufficient size to include four maximum size instructions.
Claim 12
Independent Claim 176 words
A method for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: receiving a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data; selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data; selecting a fourth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fourth plurality of sequential bytes of instruction data comprises a first instruction; and selecting a fifth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fifth plurality of sequential bytes of instruction data comprises a second instruction.
Claim 13
Independent Claim 176 words
A method for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: receiving a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data; selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data; selecting a fourth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fourth plurality of sequential bytes of instruction data comprises a first instruction; and selecting a fifth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fifth plurality of sequential bytes of instruction data comprises a second instruction.
Claim 14
Dependent Claim 158 words
A circuit for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: a first device which stores a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; a second device coupled to said first device which selects from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data wherein said second device utilizes a pointer which indicates the last byte already processed; and a third device coupled to said second device which selects a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data wherein said third device utilizes said pointer which indicates the last byte already processed.
Claim 15
Dependent Claim 158 words
A circuit for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: a first device which stores a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; a second device coupled to said first device which selects from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data wherein said second device utilizes a pointer which indicates the last byte already processed; and a third device coupled to said second device which selects a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data wherein said third device utilizes said pointer which indicates the last byte already processed.
Claim 16
Dependent Claim 21 words
The circuit of claim 11 further comprising: a pointer generator which generates said pointer to indicate the last byte already processed.
Claim 17
Dependent Claim 41 words
The circuit of claim 12 wherein said pointer generator comprises: a first decoder which determines a length for a first instruction processed; a second decoder which determines a length for a second instruction processed; and an adder which adds the lengths.
Claim 18
Dependent Claim 37 words
The circuit of claim 12 wherein said pointer generator comprises: a decoder which determines a length for each instruction of a plurality of instructions processed in a single clock cycle; and an adder which adds the lengths.
Claim 19
Dependent Claim 35 words
The circuit of claim 11 wherein said third plurality of sequential bytes of instruction data is of sufficient size to include a plurality of maximum size instructions that can be processed in one clock cycle.
Claim 20
Dependent Claim 25 words
The circuit of claim 11 wherein said third plurality of sequential bytes of instruction data is of sufficient size to include two maximum size instructions.
Claim 21
Dependent Claim 35 words
The circuit of claim 11 wherein said second plurality of sequential bytes of instruction data is of sufficient size to include a plurality of maximum size instructions that can be processed in two clock cycles.
Claim 22
Dependent Claim 25 words
The circuit of claim 11 wherein said second plurality of sequential bytes of instruction data is of sufficient size to include four maximum size instructions.
Claim 23
Dependent Claim 13 words
The circuit of claim 11 wherein said second device comprises of a multiplexor.
Claim 24
Dependent Claim 15 words
The circuit of claim 19 wherein said multiplexor comprises of a plurality of 8-to-4 mutiplexors.
Claim 25
Dependent Claim 13 words
The circuit of claim 11 wherein said third device comprises of a rotator.
Claim 26
Dependent Claim 15 words
The circuit of claim 12 wherein said rotator comprises of a plurality of 32-to-1 multiplexors.
Claim 27
Independent Claim 221 words
An apparatus for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: a first device capable of storing a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; a second device coupled to said first device capable of selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data; a third device coupled to said second device capable of selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data; a fourth device coupled to said third device capable of selecting a fourth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fourth plurality of sequential bytes of instruction data comprises a first instruction; and a fifth device coupled to said third device capable of selecting a fifth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fifth plurality of sequential bytes of instruction data comprises a second instruction.
Claim 28
Independent Claim 221 words
An apparatus for selecting a plurality of instructions from a sequence of undifferentiated bytes of instruction data comprising: a first device capable of storing a first plurality of sequential bytes of instruction data from the sequence of undifferentiated bytes of instruction data; a second device coupled to said first device capable of selecting from the first plurality of sequential bytes of instruction data a second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality of sequential bytes of instruction data; a third device coupled to said second device capable of selecting a third plurality of sequential bytes of instruction data from the second plurality of sequential bytes of instruction data beginning at any selected byte of the second plurality of sequential bytes of instruction data; a fourth device coupled to said third device capable of selecting a fourth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fourth plurality of sequential bytes of instruction data comprises a first instruction; and a fifth device coupled to said third device capable of selecting a fifth plurality of sequential bytes of instruction data from the third plurality of sequential bytes of instruction data wherein said fifth plurality of sequential bytes of instruction data comprises a second instruction.

References Cited (Backward Citations)

US4236206A Cited
US4502111A Cited
US5179680A Cited
US5202967A Cited
US5113515A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-12-03 2000-06-03 2000-12-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-12-03 2004-06-03 2004-12-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-12-03 2008-06-03 2008-12-03 $7700.00 Window Closed / Lapsed

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