Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices

Claim 1

A method for making an array of memory cells with capacitor-over-bit-line structures for dynamic random access memory (DRAM) devices on a substrate comprising the steps of: providing a semiconductor substrate having an array of field effect transistors (FETs) in each of said DRAM devices, and having gate electrodes for said FETs formed from a patterned polycide layer with a cap oxide, and each of said FETs having two adjacent source/drain areas; depositing a first polysilicon layer; patterning said first polysilicon layer to form bit lines that contact first of said source/drain areas of each of said FETs, and concurrently forming polysilicon landing pads for capacitors over and contacting second of said source/drain areas of each of said FETs; depositing and planarizing a first insulating layer; etching contact openings in said first insulating layer to said polysilicon landing pads; depositing a second polysilicon layer over said first insulating layer and filling said contact openings to form capacitor node contacts; anisotropic plasma etching using a patterned photoresist mask to etch through said second polysilicon layer and forming trenches in said first insulating layer surrounding said capacitor node contacts and defining the perimeter for desired capacitor regions for each of said memory cells, while protecting from etching said second polysilicon layer and said first insulating layer elsewhere on said DRAM devices; stripping said photomask mask; depositing a conformal third polysilicon layer over said trenches; anisotropic plasma etching back said third polysilicon layer to form sidewall spacers in said trenches for bottom electrodes of said capacitors; forming an interelectrode dielectric layer on said bottom electrodes; depositing a conformal fourth polysilicon layer for capacitor top electrodes while filling said trenches to form an essentially planar surface; etching to pattern said fourth polysilicon layer to form said capacitor top electrodes, and continuing said etching to remove said second polysilicon layer on the perimeter of said DRAM devices to complete said array of memory cells.

Claim 2

A method for making an array of memory cells with capacitor-over-bit-line structures for dynamic random access memory (DRAM) devices on a substrate comprising the steps of: providing a semiconductor substrate having an array of field effect transistors (FETs) in each of said DRAM devices, and having gate electrodes for said FETs formed from a patterned polycide layer with a cap oxide, and each of said FETs having two adjacent source/drain areas; depositing a first polysilicon layer; patterning said first polysilicon layer to form bit lines that contact first of said source/drain areas of each of said FETs, and concurrently forming polysilicon landing pads for capacitors over and contacting second of said source/drain areas of each of said FETs; depositing and planarizing a first insulating layer; etching contact openings in said first insulating layer to said polysilicon landing pads; depositing a second polysilicon layer over said first insulating layer and filling said contact openings to form capacitor node contacts; anisotropic plasma etching using a patterned photoresist mask to etch through said second polysilicon layer and forming trenches in said first insulating layer surrounding said capacitor node contacts and defining the perimeter for desired capacitor regions for each of said memory cells, while protecting from etching said second polysilicon layer and said first insulating layer elsewhere on said DRAM devices; stripping said photomask mask; depositing a conformal third polysilicon layer over said trenches; anisotropic plasma etching back said third polysilicon layer to form sidewall spacers in said trenches for bottom electrodes of said capacitors; forming an interelectrode dielectric layer on said bottom electrodes; depositing a conformal fourth polysilicon layer for capacitor top electrodes while filling said trenches to form an essentially planar surface; etching to pattern said fourth polysilicon layer to form said capacitor top electrodes, and continuing said etching to remove said second polysilicon layer on the perimeter of said DRAM devices to complete said array of memory cells.

Claim 12

A method for making dynamic random access memory (DRAM) devices having an array of memory cells with capacitor-over-bit-line structures on a substrate comprising the steps of: providing a semiconductor substrate having an array of field effect transistors (FETs) in each of said DRAM devices, and having gate electrodes for said FETs formed from a patterned polycide layer with a cap oxide, and each of said FETs having two adjacent source/drain areas; depositing a first polysilicon layer; patterning said first polysilicon layer to form bit lines that contact first of said source/drain areas of each of said FETs, and concurrently forming polysilicon landing pads for capacitors over and contacting second of said source/drain areas of each of said FETs; depositing and planarizing a first insulating layer; etching contact openings in said first insulating layer to said polysilicon landing pads; depositing a second polysilicon layer over said first insulating layer and filling said contact openings to form capacitor node contacts; anisotropic plasma etching using a patterned photoresist mask to etch through said second polysilicon layer and forming trenches in said first insulating layer surrounding said capacitor node contacts and defining the perimeter for desired capacitor regions for each of said memory cells, while protecting from etching said second polysilicon layer and said first insulating layer elsewhere on said DRAM devices; stripping said photomask mask; depositing a conformal third polysilicon layer over said trenches; anisotropic plasma etching back said third polysilicon layer to form sidewall spacers in said trenches for bottom electrodes of said capacitors; forming an interelectrode dielectric layer on said bottom electrodes; depositing a conformal fourth polysilicon layer for capacitor top electrodes while filling said trenches to form an essentially planar surface; etching to pattern said fourth polysilicon layer to form said capacitor top electrodes, and continuing said etching to remove said second polysilicon layer on the perimeter of said DRAM devices, resulting in an essentially planar surface; depositing and levelling a second insulating layer; forming contact openings in said insulating layers and forming additional levels of wiring to complete said DRAM devices.

Claim 13

A method for making dynamic random access memory (DRAM) devices having an array of memory cells with capacitor-over-bit-line structures on a substrate comprising the steps of: providing a semiconductor substrate having an array of field effect transistors (FETs) in each of said DRAM devices, and having gate electrodes for said FETs formed from a patterned polycide layer with a cap oxide, and each of said FETs having two adjacent source/drain areas; depositing a first polysilicon layer; patterning said first polysilicon layer to form bit lines that contact first of said source/drain areas of each of said FETs, and concurrently forming polysilicon landing pads for capacitors over and contacting second of said source/drain areas of each of said FETs; depositing and planarizing a first insulating layer; etching contact openings in said first insulating layer to said polysilicon landing pads; depositing a second polysilicon layer over said first insulating layer and filling said contact openings to form capacitor node contacts; anisotropic plasma etching using a patterned photoresist mask to etch through said second polysilicon layer and forming trenches in said first insulating layer surrounding said capacitor node contacts and defining the perimeter for desired capacitor regions for each of said memory cells, while protecting from etching said second polysilicon layer and said first insulating layer elsewhere on said DRAM devices; stripping said photomask mask; depositing a conformal third polysilicon layer over said trenches; anisotropic plasma etching back said third polysilicon layer to form sidewall spacers in said trenches for bottom electrodes of said capacitors; forming an interelectrode dielectric layer on said bottom electrodes; depositing a conformal fourth polysilicon layer for capacitor top electrodes while filling said trenches to form an essentially planar surface; etching to pattern said fourth polysilicon layer to form said capacitor top electrodes, and continuing said etching to remove said second polysilicon layer on the perimeter of said DRAM devices, resulting in an essentially planar surface; depositing and levelling a second insulating layer; forming contact openings in said insulating layers and forming additional levels of wiring to complete said DRAM devices.