Method and system for supporting non-deterministic burst lengths in a memory system employing extended data out(EDO)DRAM

Claim 3

The method as recited in claim 1, wherein bank select signals indicate the currently selected memory bank, and wherein said detecting comprises: comparing the bank select signals for the current access cycle to latched bank select signals; generating a bank traversal condition if said comparing indicates that the current bank select signals differ from the latched bank select signals; and latching the bank select signals for each access cycle, wherein said latching creates the latched bank select signals.

Claim 4

The method as recited in claim 1, wherein each memory bank comprises Random Access Memory (RAM) addressed by supplying a column address and latching the column address into the RAM by asserting a Column Address Strobe (CAS) signal, wherein said delaying comprises: receiving indication of said bank traversal condition; and delaying assertion of the CAS signal for a programmable amount of time upon said receiving.

Claim 5

The method as recited in claim 1, wherein said disabling comprises temporarily asserting a memory write enable signal to the memory bank selected for the immediately previous access cycle.

Claim 6

A circuit for avoiding data bus contention between a plurality of memory banks during a burst cycle to a memory page crossing a memory bank boundary, wherein each memory bank has output drivers configured to selectively drive data on a common data bus, the circuit comprising: comparison logic configured to receive bank select signals indicating which memory bank is selected for the current access cycle, and said comparison logic configured to provide a bank traversal signal, wherein said bank traversal signal is asserted when said bank select signals indicate that a different memory bank is selected for the current access cycle than was selected for the immediately previous access cycle; delay logic configured to receive said bank traversal signal and temporarily delay the continuance of the current access cycle when said bank traversal signal is asserted; and disabling logic configured to receive said bank traversal signal and assert a disable signal following assertion of said bank traversal signal, wherein the output drivers of the previously selected memory bank are disabled in response to assertion of said disable signal while leaving the memory page open within the previously selected memory bank.

Claim 7

A circuit for avoiding data bus contention between a plurality of memory banks during a burst cycle to a memory page crossing a memory bank boundary, wherein each memory bank has output drivers configured to selectively drive data on a common data bus, the circuit comprising: comparison logic configured to receive bank select signals indicating which memory bank is selected for the current access cycle, and said comparison logic configured to provide a bank traversal signal, wherein said bank traversal signal is asserted when said bank select signals indicate that a different memory bank is selected for the current access cycle than was selected for the immediately previous access cycle; delay logic configured to receive said bank traversal signal and temporarily delay the continuance of the current access cycle when said bank traversal signal is asserted; and disabling logic configured to receive said bank traversal signal and assert a disable signal following assertion of said bank traversal signal, wherein the output drivers of the previously selected memory bank are disabled in response to assertion of said disable signal while leaving the memory page open within the previously selected memory bank.

Claim 8

The circuit as recited in claim 5, wherein said comparison logic comprises: logic for latching the bank select signals for each access cycle, wherein said latching creates latched bank select signals; logic for comparing the bank select signals for the current access to cycle to the latched bank select signals; and logic for generating said bank traversal signal if said comparing indicates that the current bank select signals differ from the latched bank select signals.

Claim 9

The circuit as recited in claim 5, wherein said disable signal comprises a memory write enable signal for the memory bank selected for the immediately previous access cycle.

Claim 10

The circuit as recited in claim 7, wherein said disabling logic asserts said disable signal by temporarily asserting said memory write enable signal.

Claim 11

A memory system supporting burst access cycles crossing a memory bank boundary, comprising: a plurality of memory banks, wherein one of said plurality of memory banks is selected for each memory access cycle and wherein each memory bank has output drivers configured to selectively drive data on a common data bus; a memory controller coupled to said memory banks, said memory controller comprising: comparison logic configured to receive bank select signals indicating which memory bank is selected for the current access cycle, and said comparison logic configured to provide a bank traversal signal, wherein said bank traversal signal is asserted when said bank select signals indicate that a different memory bank is selected for the current access cycle than was selected for the immediately previous access cycle; delay logic configured to receive said bank traversal signal and temporarily delay the continuance of the current access cycle when said bank traversal signal is asserted; and disabling logic configured to receive said bank traversal signal and assert a disable signal following assertion of said bank traversal signal, wherein the output drivers of the previously selected memory bank are disabled in response to assertion of said disable signal while leaving the memory page open within the previously selected memory bank.

Claim 12

A memory system supporting burst access cycles crossing a memory bank boundary, comprising: a plurality of memory banks, wherein one of said plurality of memory banks is selected for each memory access cycle and wherein each memory bank has output drivers configured to selectively drive data on a common data bus; a memory controller coupled to said memory banks, said memory controller comprising: comparison logic configured to receive bank select signals indicating which memory bank is selected for the current access cycle, and said comparison logic configured to provide a bank traversal signal, wherein said bank traversal signal is asserted when said bank select signals indicate that a different memory bank is selected for the current access cycle than was selected for the immediately previous access cycle; delay logic configured to receive said bank traversal signal and temporarily delay the continuance of the current access cycle when said bank traversal signal is asserted; and disabling logic configured to receive said bank traversal signal and assert a disable signal following assertion of said bank traversal signal, wherein the output drivers of the previously selected memory bank are disabled in response to assertion of said disable signal while leaving the memory page open within the previously selected memory bank.

Claim 13

The memory system as recited in claim 9, wherein said comparison logic comprises: logic for latching the bank select signals for each access cycle, wherein said latching creates latched bank select signals; logic for comparing the bank select signals for the current access to cycle to the latched bank select signals; and logic for generating said bank traversal signal if said comparing indicates that the current bank select signals differ from the latched bank select signals.

Claim 14

The memory system as recited in claim 9, wherein said disable signal comprises a memory write enable signal for the memory bank selected for the immediately previous access cycle.

Claim 15

The memory system as recited in claim 11, wherein said disabling logic asserts said disable signal by temporarily asserting said memory write enable signal.

Claim 16

The memory system as recited in claim 9, wherein said memory banks comprises Random Access Memory (RAM) addressed by supplying a column address and latching the column address into the RAM by asserting a Column Address Strobe (CAS) signal.

Claim 17

The memory system as recited in claim 13, wherein said memory controller further comprises CAS controller logic for generating at least one CAS signal for each memory bank, and wherein said CAS controller logic comprises said delay logic, and wherein said delay logic delays assertion of the CAS signal for the currently selected memory bank when said bank traversal signal is asserted.

Claim 18

The memory system as recited in claim 9, wherein said memory banks comprise Extended Data Out (EDO) Dynamic Random Access Memory.

Claim 19

The memory system as recited in claim 9, wherein the length that said delay logic delays continuance of the current access cycle is programmably selected within said memory controller.