US5696924A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1997-12-09
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Expires: 2015-06-07
Abstract
Abstract A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.
Inventors
- 👤 Iain C. Robertson
- 👤 Jeffrey L. Nye
- 👤 Michael D. Asal
- 👤 Graham B. Short
- 👤 Richard D. Simpson
- 👤 James G. Littleton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:08
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/1423; G06F3/1438; G09; G09G; G09G5/00; G09G5/02; G09G5/06; G09G5/36; G09G5/363; G09G5/39; G09G5/395; G09G2360/00; G09G2360/12; G09G2360/126; G09G5/001
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
122 words
A memory access circuit for use with a computer operative to assert read and write signals and an address, the circuit comprising: a memory accessible by asserting addresses thereto; an address translator circuit having address inputs for the address supplied by the computer and outputs for supplying a translated address; and a logic circuit connected to the outputs of the address translator circuit and responsive to a write signal to automatically increment the translated address for the memory and responsive to a control signal to return to the translated address; and control circuitry connected to said logic circuit and responsive to a read signal from the computer to supply the control signal to the logic circuit to return to the translated address.
Claim 2
Dependent Claim
122 words
A memory access circuit for use with a computer operative to assert read and write signals and an address, the circuit comprising: a memory accessible by asserting addresses thereto; an address translator circuit having address inputs for the address supplied by the computer and outputs for supplying a translated address; and a logic circuit connected to the outputs of the address translator circuit and responsive to a write signal to automatically increment the translated address for the memory and responsive to a control signal to return to the translated address; and control circuitry connected to said logic circuit and responsive to a read signal from the computer to supply the control signal to the logic circuit to return to the translated address.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 further comprising graphics processor circuitry connected to said memory.
Claim 4
Independent Claim
69 words
A method of operating a memory access circuit for use with a computer operative to assert read and write signals and an address, the method comprising the steps of: translating an address from the computer to supply a translated address; automatically incrementing the translated address in response to a write signal from the computer; and returning to the translated address in response to a read signal from the computer.
Claim 5
Independent Claim
69 words
A method of operating a memory access circuit for use with a computer operative to assert read and write signals and an address, the method comprising the steps of: translating an address from the computer to supply a translated address; automatically incrementing the translated address in response to a write signal from the computer; and returning to the translated address in response to a read signal from the computer.
Claim 6
Dependent Claim
227 words
A graphics processor system comprising: a graphics processor having an address bus, a data bus and a set of control lines, said graphics processor operative to assert an address on said address bus, generate a selected one of either a read signal or a write signal on said set of control lines, and exchange data via said data bus; a memory accessible by supplying an address to an address port thereof, said memory having a data port connected to said data bus of said graphics processor; an address translator circuit having an address input connected to said address bus of said graphics processor for receiving an address and an address output connected to said address port of said memory for supplying a translated address to said address port of said memory upon receipt of an address from said address bus of said graphics processor; a logic circuit connected to said address output of said address translator circuit and to said set of control lines, said logic circuit responsive to a write signal on said set of control lines to automatically increment said translated address and responsive to a control signal to return to said translated address; and control circuitry connected to said logic circuit and said set of control lines, said control circuitry responsive to a read signal to supply said control signal to said logic circuit.
Claim 7
Dependent Claim
227 words
A graphics processor system comprising: a graphics processor having an address bus, a data bus and a set of control lines, said graphics processor operative to assert an address on said address bus, generate a selected one of either a read signal or a write signal on said set of control lines, and exchange data via said data bus; a memory accessible by supplying an address to an address port thereof, said memory having a data port connected to said data bus of said graphics processor; an address translator circuit having an address input connected to said address bus of said graphics processor for receiving an address and an address output connected to said address port of said memory for supplying a translated address to said address port of said memory upon receipt of an address from said address bus of said graphics processor; a logic circuit connected to said address output of said address translator circuit and to said set of control lines, said logic circuit responsive to a write signal on said set of control lines to automatically increment said translated address and responsive to a control signal to return to said translated address; and control circuitry connected to said logic circuit and said set of control lines, said control circuitry responsive to a read signal to supply said control signal to said logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |