Solid state temperature measurement

Claim 2

A temperature measurement system comprising M>1 current sources having respective current outputs I j , j=1,2, . . . , M, where each I j =I u +e j , I u being a fixed-valued current and e j an error current representing a deviation from said I u , means for selectively applying I j for at least one value of j to C≧1 sensors, means for measuring a voltage, V BE , at each of said sensors for each application of said currents, and means for determining for each of said sensors a value, ΔV BE , representing the difference between the voltage V BE (TOT) for V BE when the sum of all I j is selectively applied to each of said sensors and the voltage V BE (AVG) equal to the average for V BE resulting from the application to said each of said sensors of each I j individually.

Claim 3

The system of claim 1 further comprising means for generating a signal proportional to temperature at each of said sensors from the value of ΔV BE determined for each respective sensor.

Claim 4

The system of claim 2 wherein said means for generating a signal proportional to temperature comprises means for generating a signal representing T=[q*ΔV BE ]/[K*ln(M)], where q is the charge of an electron and K is Boltzmann's constant.

Claim 5

The system of claim 1, wherein the number of said sensors is C=1, and said means for selectively applying comprises means for applying each of said I j individually in sequence to said sensor and for separately applying all of said I j to said sensor at the same time.

Claim 6

The system of claim 4 wherein said sensor is a diode.

Claim 7

The system of claim 4 wherein said sensor is a transistor.

Claim 8

The system of claim 1 wherein C>1, and wherein said means for selectively applying I j comprises a multiplexer for selectively applying said I j to each of a plurality of sensors.

Claim 9

The system of claim 1 wherein at least one of said sensors is a diode.

Claim 10

The system of claim 1 wherein at least one of said sensors is a transistor.

Claim 11

The system of claim 1 wherein said means for determining is an analog-to-digital converter (ADC) having first and second input analog voltages, V BE Φ1 and V BE Φ2, respectively, and a source of reference voltage, V REF .

Claim 12

The system of claim 10, wherein said voltage reference comprises a bandgap voltage reference.

Claim 13

The system of claim 11, wherein said bandgap voltage reference comprises a resistor-diode reference network, an operational amplifier having an input offset voltage, V OSI , a switched capacitor network operating alternately in a normal mode and an auto-zero mode, said switched capacitor network storing said V OSI during said auto-zero mode, and said switched capacitor network applying said V OSI to cancel said V OSI at said input of said operational amplifier during said normal mode.

Claim 14

The system of claim 10, wherein said ADC is a sigma delta ADC comprising an input sampling circuit for sampling V BE Φ1 and V BE Φ2 during alternate clock phases, V BE Φ1 being a voltage across one of said sensors when all of said I j are applied to said sensor, V BE Φ2 being a voltage across one of said sensors when one of said I j is applied to said sensor, an integrator including an operational amplifier (op-amp) having first and second input terminals and an output terminal, said op-amp receiving input signals from said input sampling circuit on said first input terminal and a reference voltage on said second input terminal, said integrator further comprising a capacitor connected from the output terminal of said op-amp to said first input terminal, a comparator for generating an output signal when the output of said op-amp differs from a reference voltage by a predetermined amount, and a decimator for forming a count based on said output signals from said comparator.

Claim 15

The system of claim 13, wherein said op-amp is characterized by an input offset voltage, V OSI , and said ADC further comprises error correcting means operating in a first mode to sample said V OSI , and operating in a second mode for biasing said op-amp in such amount as to cancel said V OSI in the output of said ADC while measuring said first and second input signals.

Claim 16

The system of claim 14, wherein said error correcting means comprises means for adding a small positive voltage as an input to said op-amp, said small positive voltage being larger in magnitude than said V OSI .

Claim 17

The system of claim 15, wherein said means for adding comprises a capacitor selectively connected between said first terminal of said op-amp and ground.

Claim 18

The system of claim 15, wherein V BE Φ1 =V BE Φ2 when said ADC is operating in said first mode, and said decimator comprises a reversible counter operable when said ADC is operating in said first mode to register a decremented count based on the signed sum of said V OSI and said added small positive voltage, and operable when said ADC is operating in said second mode to register an incremented count based on said analog input signals, said V OSI and said added small positive voltage, said ADC operating in said second mode for at least one measurement cycle for each cycle of operation in said first mode.

Claim 19

The system of claim 15, wherein said decimator comprises a first counter for registering a first count based on the signed sum of said V OSI and said small positive voltage when said ADC is operating in said first mode, a second counter for registering a second count based on the signed sum of said first and second analog input signals to said ADC, said V OSI and said small positive voltage, and means for forming the difference between said second count and said first count.

Claim 20

The system of claim 15, wherein V BE Φ1 =V BE Φ2 when said ADC is operating in said first mode, and said decimator comprises a counter operable when said ADC is operating in said first mode to register a first count based on the signed sum of said V OSI and said added small positive voltage, and operable when said ADC is operating in said second mode to register a second count based on said analog input signals, said V OSI and said added small positive voltage, means for storing said first count, and means for forming the difference between said second count and said first count.

Claim 21

The system of claim 10, wherein said source of reference voltage comprises first and second diodes, providing respective voltages V BE1 and V BE2 when stimulated by respective applied currents, an operational amplifier (op-amp) having first and second input terminals and an output terminal, said op-amp being characterized by an input offset voltage, V OSI , a circuit arrangement having first and second modes of operation positioned intermediate said first and second diodes and said op-amp for receiving and applying voltages based on said voltages V BE1 and V BE2 to said first and second input terminals of said op-amp, said circuit arrangement comprising means operative in said first mode for applying to said op-amp a voltage which nulls said V OSI during operation in said second mode.

Claim 22

The system of claim 20, wherein said circuit arrangement comprises a switched network storing said V OSI during said first mode, and said switched capacitor network applying said stored V OSI to substantially cancel said V OSI at said input of said operational amplifier during operation in said second mode.

Claim 23

The system of claim 21, further comprising means for alternating between said first and second modes of operation, said first mode of operation becoming the active mode at a time when the cancellation of said V OSI is about to deteriorate to an unacceptable level.

Claim 24

The system of claim 21 wherein said means for alternating comprises a logic arrangement responsive to an applied periodic signal, the period of said periodic signal being chosen based on the deterioration of said stored V OSI .

Claim 25

A temperature measurement method comprising selectively applying M>1 currents I j , j=1,2, . . . , M, where each I j =I u +e j , I u being a fixed-valued current and e j an error current representing a deviation from said I u , to C≧1 sensors, measuring a voltage, V BE , at each of said sensors for each said applying of current, and determining a value, ΔV BE , representing the difference between the voltage V BE (TOT) for V BE when the sum of all I j is selectively applied to each of said sensors and the voltage V BE (AVG) equal to the average for V BE resulting from the application to said each of said sensors of each I j individually.

Claim 26

A temperature measurement method comprising selectively applying M>1 currents I j , j=1,2, . . . , M, where each I j =I u +e j , I u being a fixed-valued current and e j an error current representing a deviation from said I u , to C≧1 sensors, measuring a voltage, V BE , at each of said sensors for each said applying of current, and determining a value, ΔV BE , representing the difference between the voltage V BE (TOT) for V BE when the sum of all I j is selectively applied to each of said sensors and the voltage V BE (AVG) equal to the average for V BE resulting from the application to said each of said sensors of each I j individually.

Claim 27

The method of claim 24, wherein the number of said sensors is C=1, and said selectively applying comprises applying each of said I j individually in sequence to said sensor and for separately applying all of said I j to said sensor at the same time.

Claim 28

The method of claim 24 further comprising generating a signal proportional to temperature at each of said sensors from the value of ΔV BE determined for each respective sensor.

Claim 29

The method of claim 26 wherein said generating a signal proportional to temperature comprises generating a signal representing T=[q*ΔV BE ]/[K*ln(M)], where q is the charge of an electron and K is Boltzmann's constant.