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US4600901A
Expired / Lapsed
US
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Switched capacitance feedback control circuit and sigma-delta modulator using same
Assignee: Alcatel Lucent NV
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Filing: 1985-03-14
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Granted: 1986-07-15
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Expires: 2005-03-14
Abstract
Abstract The present invention discloses a feedback control circuit in which the input and feedback signals are processed by making use of the same capacitance so that there is no problem of capacitance matching. Another aspect of the invention is a sigma-delta modulator in which the processing means includes integration means which are able to integrate said sampled and added input and feedback signals and to provide an analog output signal, a one-bit analog-to-digital converter providing a digital output signal in response to said analog output signal, and a one-bit digital-to-analog converter providing said feedback signal in response to said output signal, said input signal being sampled and simultaneously said converters being operated by and during first of said timing signals, while by and during second of said timing signals said feedback signal is sampled and said input and feedback signals are added and integrated, said first and second timing signals being non-overlapping and defining a sampling period. Thus a relatively long time is available for the sampling of the input and feedback signals as well as for the operation of the converters, even when the sampling period is relatively short.
Inventors
- 👤 Dirk H. L. C. Rabaey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:06
CPC Classifications
H; H03; H03H; H03H19/00; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/324; H03M3/346; H03M3/02; H03M3/368; H03M3/37; H03M3/374; H03M3/39; H03M3/412; H03M3/422; H03M3/43; H03M3/436; H03M3/438
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
202 words
A sigma-delta modulator for digitally encoding an analog input signal, comprising: switched capacitance feedback control circuit means including a cascade connection of switched capacitance signal input means and signal processing means, said input means further including timing means for providing timing signals, a single capacitance means and switching means controlled by said timing means, such that said input means samples and algebraically adds an analog input signal and an analog feedback signal coupled thereto by said processing means; and such that said processing means includes integration means for integrating said sampled and added input [x(t)] and feedback signals and to provide an analog output signal [w(t)]; a one-bit analog-to-digital converter means providing a digital output signal (z) in response to said analog output signal, and a one-bit digital-to-analog converter means for providing said feedback signal in response to said output signal [w(t)], said input signal [x(t)] being sampled and wherein said converters being simultaneously operated by and during the first of said timing signals, and during the second of said timing signals said feedback signal is sampled and said input and feedback signals are added and integrated, and whereby said first and second timing signals are non-overlapping and define a sampling period.
Claim 2
Dependent Claim
202 words
A sigma-delta modulator for digitally encoding an analog input signal, comprising: switched capacitance feedback control circuit means including a cascade connection of switched capacitance signal input means and signal processing means, said input means further including timing means for providing timing signals, a single capacitance means and switching means controlled by said timing means, such that said input means samples and algebraically adds an analog input signal and an analog feedback signal coupled thereto by said processing means; and such that said processing means includes integration means for integrating said sampled and added input [x(t)] and feedback signals and to provide an analog output signal [w(t)]; a one-bit analog-to-digital converter means providing a digital output signal (z) in response to said analog output signal, and a one-bit digital-to-analog converter means for providing said feedback signal in response to said output signal [w(t)], said input signal [x(t)] being sampled and wherein said converters being simultaneously operated by and during the first of said timing signals, and during the second of said timing signals said feedback signal is sampled and said input and feedback signals are added and integrated, and whereby said first and second timing signals are non-overlapping and define a sampling period.
Claim 3
Dependent Claim
117 words
A sigma-delta modulator according to claim 1, wherein said integration means includes an operational amplifier means having a feedback second capacitance and a non-inverting input connected to a reference voltage; and said switching means includes a first and a second switch for connecting said input signal and said feedback signal to one plate of said single capacitance means respectively, and a third and a fourth switch for connecting the other plate of said first capacitance means to said reference voltage sand to the inverting input of said operational amplifier respectively, such that said first and third switches are activated by said first timing signals and said second and fourth switches are activated by said second timing signals.
Claim 4
Dependent Claim
63 words
A sigma-delta modulator according to claim 1, wherein said one-bit analog-to-digital converter includes. a sampling circuit means which is activated by said second timing signals for sampling said output signal and a reference signal (ground); and a comparator circuit which is activated by said first timing signals for comparing said sampled output and reference (ground) signals to provide said digital output signal (z).
Claim 5
Dependent Claim
52 words
A sigma-delta modulator according to claim 1, wherein said digital-to-analog converter is comprised of a gating circuit means which provides at its output said feedback signal equal either to a second reference signal (V) or to the inverse (-V) thereof when said digital output signal (z) is either 1 or 0 respectively.
Claim 6
Dependent Claim
25 words
A sigma-delta modulator according to claim 1, wherein said first and second timing signals each have a duration equal to 3/8 of a sampling period.
Claim 7
Dependent Claim
37 words
A sigma-delta modulator according to claim 1, further including: second digital input means and second integration means for sampling, adding and integrating a second input signal u(t) and said feedback signal to provide said first input signal.
References Cited (Backward Citations)
US4504803A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-14 | 1990-01-13 | 1990-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-14 | 1994-01-13 | 1994-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-14 | 1998-01-13 | 1998-07-15 | $7700.00 | Window Closed / Lapsed |