US6008523A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical fuses with tight pitches and method of fabrication in semiconductors
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-08-26
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Granted: 1999-12-28
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Expires: 2018-08-26
Abstract
Abstract A semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. The semiconductor device includes a substrate with a tight pitch array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each connected at one end to an individual connector terminal of larger cross sectional area than that of the fuse link, and at another end to a common connector terminal of larger cross sectional area than that of the individual connector terminals. The common connector terminal is typically held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link. The common connector terminal cross sectional area is desirably about 2 or more times that of the individual fuse links to enable electrical fusing at voltages of about 10 volts or less.
Inventors
- 👤 Chandrasekhar Narayan
- 👤 Axel Brintzinger
- 👤 Gabriel Daniel
- 👤 Fred Einspruch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:33
CPC Classifications
H; H10; H10D; H10D99/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
77 words
A semiconductor device comprising: a substrate having on a surface thereof an array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each being connected at one end thereof to an individual connector terminal of larger cross sectional area than that of the fuse link, and being connected at another end thereof to a common connector terminal of larger cross sectional area than that of the individual connector terminals.
Claim 2
Dependent Claim
77 words
A semiconductor device comprising: a substrate having on a surface thereof an array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each being connected at one end thereof to an individual connector terminal of larger cross sectional area than that of the fuse link, and being connected at another end thereof to a common connector terminal of larger cross sectional area than that of the individual connector terminals.
Claim 3
Dependent Claim
40 words
The semiconductor device of claim 1 wherein the cross sectional area of the common connector terminal is at least about 2 times that of the individual fuse links for enabling electrical fusing at voltages of at most about 10 volts.
Claim 4
Dependent Claim
53 words
The semiconductor device of claim 1 wherein the common connector terminal is held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.
Claim 5
Dependent Claim
24 words
The semiconductor device of claim 1 wherein the common connector terminal is locally notched at the point of connection of each fuse link thereto.
Claim 6
Dependent Claim
104 words
The semiconductor device of claim 1 further comprising a plurality of layers of insulation material such that the array of fuses is encapsulated between two layers of insulation material of the plurality of layers of insulation material, one of the two layers being disposed in underlying relation to the array of fuses and the other of the two layers being disposed in overlying relation to the array of fuses, and electrical contacts formed in respective openings of the layer of insulation material in overlying relation to the array of fuses, which openings correspondingly expose portions of the individual connector terminals and common connector terminal.
Claim 7
Dependent Claim
49 words
The semiconductor device of claim 1 wherein the fuse links have a cross sectional area of about 0.02-0.3 square micron, the individual connector terminals have a cross sectional area of about 0.1-1.5 square microns, and the common connector terminal has a cross sectional area of about 0.2-3 square microns.
Claim 8
Dependent Claim
147 words
A semiconductor device comprising: a substrate having on a surface thereof a bank of electrical fuses in an array for redundancy activation wiring or custom wiring, including a plurality of fuse links each connected at one end thereof to an individual connector terminal of larger cross sectional area than that of the fuse link and at another end thereof to a common connector terminal of larger cross sectional area than that of the individual connector terminals to promote maximized differential resistance heating between the common connector terminal and each corresponding fuse link and maximized preferential melting of each said fuse link, the common connector terminal being held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.
Claim 9
Dependent Claim
147 words
A semiconductor device comprising: a substrate having on a surface thereof a bank of electrical fuses in an array for redundancy activation wiring or custom wiring, including a plurality of fuse links each connected at one end thereof to an individual connector terminal of larger cross sectional area than that of the fuse link and at another end thereof to a common connector terminal of larger cross sectional area than that of the individual connector terminals to promote maximized differential resistance heating between the common connector terminal and each corresponding fuse link and maximized preferential melting of each said fuse link, the common connector terminal being held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.
Claim 10
Dependent Claim
40 words
The semiconductor device of claim 7 wherein the cross sectional area of the common connector terminal is at least about 2 times that of the individual fuse links for enabling electrical fusing at voltages of at most about 10 volts.
Claim 11
Dependent Claim
24 words
The semiconductor device of claim 7 wherein the common connector terminal is locally notched at the point of connection of each fuse link thereto.
Claim 12
Dependent Claim
104 words
The semiconductor device of claim 7 further comprising a plurality of layers of insulation material such that the array of fuses is encapsulated between two layers of insulation material of the plurality of layers of insulation material, one of the two layers being disposed in underlying relation to the array of fuses and the other of the two layers being disposed in overlying relation to the array of fuses, and electrical contacts formed in respective openings of the layer of insulation material in overlying relation to the array of fuses, which openings correspondingly expose portions of the individual connector terminals and common connector terminal.
Claim 13
Dependent Claim
49 words
The semiconductor device of claim 7 wherein the fuse links have a cross sectional area of about 0.02-0.3 square micron, the individual connector terminals have a cross sectional area of about 0.1-1.5 square microns, and the common connector terminal has a cross sectional area of about 0.2-3 square microns.
Claim 14
Dependent Claim
222 words
A semiconductor device comprising a substrate having on a surface thereof an array of redundancy activation wiring and/or custom wiring fuses comprising: a plurality of individual connector terminals of selective cross sectional area, each extending longitudinally from a distal end thereof to a medial end thereof and being in closely adjacent side by side arrangement; a fuse link extending from the medial end of each individual connector terminal and being of smaller cross sectional area than that of the individual connector terminals; and a common connector terminal of larger cross sectional area than that of each individual connector terminal to promote maximized differential resistance heating between the common connector terminal and each corresponding fuse link and maximized preferential melting of each said fuse link, the common connector terminal extending crosswise of the side by side arrangement of the individual connector terminals and being connected along its length to each adjacent fuse link; the cross sectional area of the common connector terminal being at least about 2 times that of the individual fuse links; and the common connector terminal being arranged for connection at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.
Claim 15
Dependent Claim
222 words
A semiconductor device comprising a substrate having on a surface thereof an array of redundancy activation wiring and/or custom wiring fuses comprising: a plurality of individual connector terminals of selective cross sectional area, each extending longitudinally from a distal end thereof to a medial end thereof and being in closely adjacent side by side arrangement; a fuse link extending from the medial end of each individual connector terminal and being of smaller cross sectional area than that of the individual connector terminals; and a common connector terminal of larger cross sectional area than that of each individual connector terminal to promote maximized differential resistance heating between the common connector terminal and each corresponding fuse link and maximized preferential melting of each said fuse link, the common connector terminal extending crosswise of the side by side arrangement of the individual connector terminals and being connected along its length to each adjacent fuse link; the cross sectional area of the common connector terminal being at least about 2 times that of the individual fuse links; and the common connector terminal being arranged for connection at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.
Claim 16
Dependent Claim
24 words
The semiconductor device of claim 12 wherein the common connector terminal is locally notched at the point of connection of each fuse link thereto.
Claim 17
Dependent Claim
104 words
The semiconductor device of claim 12 further comprising a plurality of layers of insulation material such that the array of fuses is encapsulated between two layers of insulation material of the plurality of layers of insulation material, one of the two layers being disposed in underlying relation to the array of fuses and the other of the two layers being disposed in overlying relation to the array of fuses, and electrical contacts formed in respective openings of the layer of insulation material in overlying relation to the array of fuses, which openings correspondingly expose portions of the individual connector terminals and common connector terminal.
Claim 18
Dependent Claim
49 words
The semiconductor device of claim 12 wherein the fuse links have a cross sectional area of about 0.02-0.3 square micron, the individual connector terminals have a cross sectional area of about 0.1-1.5 square microns, and the common connector terminal has a cross sectional area of about 0.2-3 square microns.
Claim 19
Dependent Claim
76 words
An array of fuses on a surface of a substrate of a semiconductor device including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each being connected at one end thereof to an individual connector terminal of larger cross sectional area than that of the fuse link, and being connected at another end thereof to a common connector terminal of larger cross sectional area than that of the individual connector terminals.
Claim 20
Dependent Claim
76 words
An array of fuses on a surface of a substrate of a semiconductor device including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each being connected at one end thereof to an individual connector terminal of larger cross sectional area than that of the fuse link, and being connected at another end thereof to a common connector terminal of larger cross sectional area than that of the individual connector terminals.
Claim 21
Dependent Claim
50 words
The array of fuses of claim 16 wherein the fuse links have a cross sectional area of about 0.02-0.3 square micron, the individual connector terminals have a cross sectional area of about 0.1-1.5 square microns, and the common connector terminal has a cross sectional area of about 0.2-3 square microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |