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Patent US6006166A successfully refreshed from Google Patents.
US6006166A
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Apparatus for testing a controller with random constraints
Assignee: Micron Technology Inc
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Filing: 1998-05-05
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Granted: 1999-12-21
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Expires: 2018-05-05
Abstract
Abstract An apparatus for testing an IDE controller with random constraints, the apparatus including: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes at least one channel and a host interface; a control module for generating data patterns and for transmitting and receiving the data patterns via the host interface and the at least one channel; a verification module, coupled to the control module, for determining whether received data patterns match expected values; and a device module, coupled to the at least one channel, for receiving the data patterns transmitted from the control module and transmitting the data patterns back to the verification module via the at least one channel.
Inventors
- 👤 James W. Meyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F2213/00; G06F2213/38; G06F2213/3802; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/0614; G06F3/0628; G06F3/0655; G06F3/0658
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
77 words
A system for testing an IDE controller comprising: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes primary and secondary channels and a host interface; a primary control module, coupled to the host interface, for testing the primary channel; a secondary control module, coupled to the host interface, for testing the secondary channel; and a host request module for arbitrating access to the host interface between the primary and secondary control modules.
Claim 2
Independent Claim
77 words
A system for testing an IDE controller comprising: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes primary and secondary channels and a host interface; a primary control module, coupled to the host interface, for testing the primary channel; a secondary control module, coupled to the host interface, for testing the secondary channel; and a host request module for arbitrating access to the host interface between the primary and secondary control modules.
Claim 3
Dependent Claim
28 words
The system of claim 1 wherein the host request module arbitrates the transmission of the data patterns across the host interface on a first come, first served basis.
Claim 4
Dependent Claim
129 words
The system of claim 1 wherein: the primary control module includes a primary random number generator module for generating a primary random binary number having a specified number of bits, wherein a primary random test constraint is represented by at least one bit of the primary random binary number, and primary data patterns are transmitted across the IDE controller in accordance with the primary random test constraint; and the secondary control module includes a secondary random number generator module for generating a secondary random binary number having a specified number of bits, wherein a secondary random test constraint is represented by at least one bit of the secondary random binary number, and secondary data patterns are transmitted across the IDE controller in accordance with the secondary random test constraint.
Claim 5
Dependent Claim
46 words
The system of claim 3 wherein said primary data patterns are random data patterns represented by at least one bit of the primary random binary number and secondary data patterns are random data patterns represented by at least one bit of the secondary random binary number.
Claim 6
Dependent Claim
106 words
The system of claim 4 further comprising: a primary device module, coupled to the primary channel, for simulating a primary IDE device, wherein said primary control module further comprises a primary verification module, coupled to the primary control module, for determining whether the primary data pattern returned from the primary device module matches an expected value; and a secondary device module, coupled to the secondary channel for simulating a secondary IDE device, wherein said secondary control module further comprises a secondary verification module, coupled to the secondary device module, for determining whether the secondary data pattern returned from the secondary device module matches an expected value.
Claim 7
Dependent Claim
31 words
The system of claim 5 wherein the host request module arbitrates the transmission of the primary and secondary data patterns across the host interface on a first come, first served basis.
Claim 8
Dependent Claim
19 words
The system of claim 3 wherein each of the primary and secondary random binary numbers is a 32-bit dataword.
Claim 9
Independent Claim
113 words
A system for testing an IDE controller comprising: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes at least one channel and a host interface; a control module for generating data patterns and for transmitting and receiving the data patterns via the host interface and the at least one channel; a verification module, coupled to the control module, for determining whether received data patterns match expected values; and a device module, coupled to the at least one channel, for receiving the data patterns transmitted from the control module and transmitting the data patterns back to the verification module via the at least one channel and the host interface.
Claim 10
Independent Claim
113 words
A system for testing an IDE controller comprising: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes at least one channel and a host interface; a control module for generating data patterns and for transmitting and receiving the data patterns via the host interface and the at least one channel; a verification module, coupled to the control module, for determining whether received data patterns match expected values; and a device module, coupled to the at least one channel, for receiving the data patterns transmitted from the control module and transmitting the data patterns back to the verification module via the at least one channel and the host interface.
Claim 11
Dependent Claim
19 words
The system of claim 8 further comprising a host request module for controlling data traffic across said host interface.
Claim 12
Dependent Claim
50 words
The system of claim 8 wherein the control module further generates random test constraints and programs the at least one channel of the IDE controller with the random test constraints such that the data patterns are communicated to and from the device module in accordance with the random test constraints.
Claim 13
Dependent Claim
18 words
The system of claim 8 wherein the data patterns are random data patterns generated by the control module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |