Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
107 words
A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously, comprising: providing said integrated circuit substrate surface on a polishing pad mounted on an anode including an electrolyzable conductive material; connecting a first electrical connection of a voltage source to said anode and connecting a second electrical connection of said voltage source to said integrated circuit substrate; introducing on said polishing pad slurry admixed with an electrolyte; and polishing the integrated circuit substrate surface while applying a voltage between said integrated circuit substrate and said anode such that said conductive material is deposited on the integrated circuit substrate surface.
Claim 2
Dependent Claim
107 words
A process of depositing a conductive material on and polishing a surface of an integrated circuit substrate simultaneously, comprising: providing said integrated circuit substrate surface on a polishing pad mounted on an anode including an electrolyzable conductive material; connecting a first electrical connection of a voltage source to said anode and connecting a second electrical connection of said voltage source to said integrated circuit substrate; introducing on said polishing pad slurry admixed with an electrolyte; and polishing the integrated circuit substrate surface while applying a voltage between said integrated circuit substrate and said anode such that said conductive material is deposited on the integrated circuit substrate surface.
Claim 3
Dependent Claim
13 words
The process of claim 1, wherein said anode includes at least one metal.
Claim 4
Dependent Claim
14 words
The process of claim 1, wherein said anode is mounted on a supporting body.
Claim 5
Dependent Claim
12 words
The process of claim 3, wherein said supporting body is a platen.
Claim 6
Dependent Claim
85 words
The process of claim 1, wherein: said integrated circuit substrate is a semiconductor wafer having a surface that includes a dielectric layer having an aperture and a trench, said aperture provides an opening from a top surface to a bottom surface of said dielectric layer and said trench is a concave region that recesses inwardly into said top surface of said dielectric layer and is disposed above said aperture; and in said applying voltage said conductive material is deposited in said aperture and said trench.
Claim 7
Dependent Claim
21 words
The process of claim 5, wherein said aperture has a depth that is between about 500 Angstroms and about 3 μm.
Claim 8
Dependent Claim
21 words
The process of claim 5, wherein said aperture has a width that is between about 250 Angstroms and about 1 μm.
Claim 9
Dependent Claim
21 words
The process of claim 5, wherein said trench has a depth that is between about 500 Angstroms and about 2 μm.
Claim 10
Dependent Claim
21 words
The process of claim 5, wherein said trench has a width that is between about 500 Angstroms and about 1 μm.
Claim 11
Dependent Claim
17 words
The process of claim 9, wherein said width is between about 500 Angstroms and about 0.25 μm.
Claim 12
Dependent Claim
15 words
The process of claim 5, wherein a metallization layer is disposed below said dielectric layer.
Claim 13
Dependent Claim
36 words
The process of claim 5, wherein said connecting said second electrical connection to said integrated circuit substrate includes securing said integrated circuit substrate on a substrate holder that is electrically connected to said second electrical connection.
Claim 14
Dependent Claim
16 words
The process of claim 1, wherein said anode is one of metallic disk or metallic ring.
Claim 15
Dependent Claim
61 words
The process of claim 1, wherein in said applying, said voltage is sufficiently high to deposit a thickness of said conductive material on the integrated circuit substrate surface and in said polishing, a pressure exerted by the integrated circuit substrate on the polishing pad is sufficiently high to remove said conductive material of said thickness from said integrated circuit substrate surface.