Method for silicide stringer removal in the fabrication of semiconductor integrated circuits

Claim 1

A method of forming a MOS integrated circuit, comprising the steps of: providing a gate electrode structure; forming a sidewall spacer adjacent each opposite sidewall of said gate electrode structure, said sidewall spacer being formed of a material selected from the group consisting of silicon oxide, phosphorus doped silicon oxide and silicon nitride, each spacer overlying a portion of a source region or a drain region proximate said gate electrode structure; depositing a metal layer overlying exposed portions of said gate electrode structure, source and drain regions and sidewall spacers, wherein said metal layer is a silicide forming material; forming metal silicide regions coincident to said exposed portions of said source and drain regions; removing unreacted metal of said metal layer; and etching said sidewall spacers, wherein at least a portion of said sidewall spacers is etched away.

Claim 2

A method of forming a MOS integrated circuit, comprising the steps of: providing a gate electrode structure; forming a sidewall spacer adjacent each opposite sidewall of said gate electrode structure, said sidewall spacer being formed of a material selected from the group consisting of silicon oxide, phosphorus doped silicon oxide and silicon nitride, each spacer overlying a portion of a source region or a drain region proximate said gate electrode structure; depositing a metal layer overlying exposed portions of said gate electrode structure, source and drain regions and sidewall spacers, wherein said metal layer is a silicide forming material; forming metal silicide regions coincident to said exposed portions of said source and drain regions; removing unreacted metal of said metal layer; and etching said sidewall spacers, wherein at least a portion of said sidewall spacers is etched away.

Claim 12

A method for forming a MOS transistor with silicide stringers removed, comprising the steps of: providing a semiconductor wafer having an upper surface comprised of silicon; forming an isolation region in said wafer, wherein an active area, adjacent said upper surface, is defined by said isolation region; forming a gate dielectric overlying at least a portion of said active area; forming a gate electrode overlying said gate dielectric; forming a source region and a drain region, in said active area, adjacent opposite sidewalls of said gate electrode; forming sidewall spacers adjacent each of said opposite sidewalls and overlying a portion of said source and drain regions, said sidewall spacers being formed of a material selected from the group consisting of silicon oxide, phosphorus doped silicon oxide and silicon nitride; depositing a blanket silicide forming metal layer overlying said semiconductor wafer, wherein said metal layer is in contact with the silicon of an upper surface of said source and drain regions; heating said substrate to a first temperature, wherein said first temperature is sufficiently high for said metal layer to react to form metal silicide regions; selectively etching said metal layer, wherein unreacted metal of said metal layer is removed; and etching said sidewall spacers, wherein at least a portion of said sidewall spacers is etched away.

Claim 13

A method for forming a MOS transistor with silicide stringers removed, comprising the steps of: providing a semiconductor wafer having an upper surface comprised of silicon; forming an isolation region in said wafer, wherein an active area, adjacent said upper surface, is defined by said isolation region; forming a gate dielectric overlying at least a portion of said active area; forming a gate electrode overlying said gate dielectric; forming a source region and a drain region, in said active area, adjacent opposite sidewalls of said gate electrode; forming sidewall spacers adjacent each of said opposite sidewalls and overlying a portion of said source and drain regions, said sidewall spacers being formed of a material selected from the group consisting of silicon oxide, phosphorus doped silicon oxide and silicon nitride; depositing a blanket silicide forming metal layer overlying said semiconductor wafer, wherein said metal layer is in contact with the silicon of an upper surface of said source and drain regions; heating said substrate to a first temperature, wherein said first temperature is sufficiently high for said metal layer to react to form metal silicide regions; selectively etching said metal layer, wherein unreacted metal of said metal layer is removed; and etching said sidewall spacers, wherein at least a portion of said sidewall spacers is etched away.