Spacer-type thin-film polysilicon transistor for low-power memory devices

Claim 2

A thin-film transistor (TFT) structure having a reduced cross-sectional channel area in order to minimize bitline to supply leakage of the TFT, comprising: a substrate; a TFT polysilicon gate formed on top of the substrate; a gate oxide layer formed over the substrate and the TFT polysilicon gate; a TFT polysilicon channel formed adjacent to a side of the TFT polysilicon gate, wherein the TFT polysilicon channel has a channel thickness which is limited by the thickness of a deposited channel polysilicon layer which has been selectively removed leaving only the TFT polysilicon channel and wherein the TFT polysilicon channel has a channel width that corresponds to the height of the TFT polysilicon channel etched along the TFT polysilicon gate.

Claim 3

The structure of claim 1, wherein the channel thickness is approximately 300 to 500 Å and the channel width is approximately 0.15 to 0.25 μm.

Claim 4

The structure of claim 1, wherein the channel thickness and the channel width of the TFT polysilicon channel are adjusted by modifying the thickness of the TFT polysilicon gate.

Claim 5

A thin-film transistor (TFT) structure having a reduced cross-sectional channel area in order to minimize bitline to supply leakage of the TFT, comprising: an isolation region adjacent to an active region; a polysilicon gate region formed over the active region and a first portion of the isolation region, wherein the active region is adjacent to the first portion of the isolation region; a first oxide layer formed over a first portion of the active region and over a second portion of the isolation region; an opening formed in the first oxide layer over a third portion of the isolation region adjacent to an end of the polysilicon gate region; a second oxide layer formed over the first oxide layer, the polysilicon gate region, and the opening formed in the first oxide layer; and a TFT polysilicon channel formed in the opening of the first oxide layer adjacent to the end of the polysilicon gate region, wherein the TFT polysilicon channel has a channel thickness which is limited by the thickness of a deposited channel polysilicon layer which has been selectively removed.

Claim 6

A thin-film transistor (TFT) structure having a reduced cross-sectional channel area in order to minimize bitline to supply leakage of the TFT, comprising: an isolation region adjacent to an active region; a polysilicon gate region formed over the active region and a first portion of the isolation region, wherein the active region is adjacent to the first portion of the isolation region; a first oxide layer formed over a first portion of the active region and over a second portion of the isolation region; an opening formed in the first oxide layer over a third portion of the isolation region adjacent to an end of the polysilicon gate region; a second oxide layer formed over the first oxide layer, the polysilicon gate region, and the opening formed in the first oxide layer; and a TFT polysilicon channel formed in the opening of the first oxide layer adjacent to the end of the polysilicon gate region, wherein the TFT polysilicon channel has a channel thickness which is limited by the thickness of a deposited channel polysilicon layer which has been selectively removed.

Claim 7

The structure of claim 4, wherein the channel thickness is approximately 300 to 500 Å and a channel width of the TFT polysilicon channel is approximately 0.15 to 0.25 μm.

Claim 8

The structure of claim 4, wherein the channel thickness and the channel width of the TFT polysilicon channel are adjusted by modifying the thickness of the polysilicon gate region.