← Back to Patent Explorer
US5841173A Expired / Lapsed US ⏱️ 0.0 years remaining

MOS semiconductor device with excellent drain current

Assignee: Panasonic Holdings Corp
•
Filing: 1996-06-13
•
Granted: 1998-11-24
•
Expires: 2016-06-13
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A MOS semiconductor device includes a first conductivity type silicon layer having a main surface; a gate insulating film selectively formed on the main surface of the silicon layer; a gate electrode provided on the gate insulating film; an insulating side wall formed on the side of the gate electrode; and source/drain regions formed in the silicon layer. The source/drain regions include a first diffusion layer of second conductivity type formed in the silicon layer; a second diffusion layer of second conductivity type formed in the silicon layer on the outside of the first diffusion layer and having a PN-junction depth larger than that of the first diffusion layer; and the MOS semiconductor device further includes a conductive layer covering at least part of the first diffusion layer and at least part of the second diffusion layer.

Inventors

  • 👤 Kyoji Yamashita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 02:04
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0215; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/015

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 182 words
A MOS semiconductor device, comprising: a first conductivity type silicon layer having a main surface; a gate insulating film selectively formed on said main surface of said silicon layer; a gate electrode provided on the gate insulating film; an insulating side wall formed on the side of said gate electrode; and source/drain regions formed in said silicon layer; wherein said source/drain regions comprise: a first diffusion layer of second conductivity type formed in said silicon layer; and a second diffusion layer of second conductivity type formed in said silicon layer on the outside of said first diffusion layer and having a PN-junction depth larger than that of said first diffusion layer; wherein said MOS semiconductor device further comprises a conductive layer covering at least part of said first diffusion layer and at least part of said second diffusion layer; wherein said conductive layer comprises a first part having a first thickness and a second part having a second thickness larger than said first thickness; and said first part of said conductive layer covers said at least part of said second diffusion layer.
Claim 2
Dependent Claim 182 words
A MOS semiconductor device, comprising: a first conductivity type silicon layer having a main surface; a gate insulating film selectively formed on said main surface of said silicon layer; a gate electrode provided on the gate insulating film; an insulating side wall formed on the side of said gate electrode; and source/drain regions formed in said silicon layer; wherein said source/drain regions comprise: a first diffusion layer of second conductivity type formed in said silicon layer; and a second diffusion layer of second conductivity type formed in said silicon layer on the outside of said first diffusion layer and having a PN-junction depth larger than that of said first diffusion layer; wherein said MOS semiconductor device further comprises a conductive layer covering at least part of said first diffusion layer and at least part of said second diffusion layer; wherein said conductive layer comprises a first part having a first thickness and a second part having a second thickness larger than said first thickness; and said first part of said conductive layer covers said at least part of said second diffusion layer.
Claim 3
Dependent Claim 21 words
A MOS semiconductor device according to claim 1, wherein said silicon layer is formed on a substrate having an insulating surface.
Claim 4
Dependent Claim 16 words
A MOS semiconductor device according to claim 1, wherein said conductive layer is formed of silicide.
Claim 5
Dependent Claim 26 words
A MOS semiconductor device according to claim 1, wherein said gate electrode has a multi-layer structure comprising a lower silicon film and an upper silicide film.
Claim 6
Dependent Claim 19 words
A MOS semiconductor device according to claim 1, wherein said silicon layer is formed of a single crystalline semiconductor.

References Cited (Backward Citations)

US4821085A Cited
US5113234A Cited
US5068696A Cited
US5341028A Cited
US5091763A Cited
US5635746A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-11-23 2002-05-25 2002-11-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-11-23 2006-05-25 2006-11-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-11-23 2010-05-25 2010-11-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag