Method of manufacturing semiconductor device having a fuse

Claim 1

A method of manufacturing a semiconductor device, comprising the steps of: forming a fuse layer connected to a redundant circuit; forming an interlayer insulating layer to cover said fuse layer; forming a concave portion on a surface of said interlayer insulating layer located directly above said fuse layer, having a first opening width (W1) larger than the two-dimensional width of said fuse layer; forming a passivation layer to cover said concave portion and said interlayer insulating layer; forming a mask layer on said passivation layer, provided with a first opening with a second opening width (W2) smaller than said first opening width (W1) directly above said fuse layer; and forming a second opening in said passivation layer, exposing a bottom surface of said concave portion located directly above said fuse layer by etching said passivation layer using said mask layer as a mask.

Claim 2

A method of manufacturing a semiconductor device, comprising the steps of: forming a fuse layer connected to a redundant circuit; forming an interlayer insulating layer to cover said fuse layer; forming a concave portion on a surface of said interlayer insulating layer located directly above said fuse layer, having a first opening width (W1) larger than the two-dimensional width of said fuse layer; forming a passivation layer to cover said concave portion and said interlayer insulating layer; forming a mask layer on said passivation layer, provided with a first opening with a second opening width (W2) smaller than said first opening width (W1) directly above said fuse layer; and forming a second opening in said passivation layer, exposing a bottom surface of said concave portion located directly above said fuse layer by etching said passivation layer using said mask layer as a mask.

Claim 3

A method of manufacturing a semiconductor device, comprising the steps of: forming a fuse layer connected to a redundant circuit; forming an interlayer insulating layer to cover said fuse layer; forming a bonding pad layer on said interlayer insulating layer not to overlap said fuse layer; forming a first insulating layer having a first relative dielectric constant and constituting a part of a passivation layer to cover said bonding pad layer and said interlayer insulating layer; forming, in said first insulating layer, a first opening with a first opening width (W1) penetrating said first insulating layer located directly above said fuse layer, and a second opening penetrating said first insulating layer to selectively expose a surface of said bonding pad layer, and forming a concave portion having sidewalls connected to sidewalls of said first opening and a bottom surface in said interlayer insulating layer on a surface of said interlayer insulating layer; forming a second insulating layer having a second relative dielectric constant higher than said first relative dielectric constant and constituting a portion of said passivation layer on said first insulating layer to cover said first and second openings and said concave portion; forming a mask layer on said second insulating layer, provided with a third opening with a second opening width (W2) smaller than said first opening width (W1) directly above said fuse layer, and provided with a fourth opening on said second opening; and forming a fifth opening exposing a bottom surface of said concave portion located directly above said fuse layer, and a sixth opening selectively exposing the surface of said bonding pad layer by etching said second insulating layer using said mask layer as a mask.

Claim 4

A method of manufacturing a semiconductor device, comprising the steps of: forming a fuse layer connected to a redundant circuit; forming an interlayer insulating layer to cover said fuse layer; forming a bonding pad layer on said interlayer insulating layer not to overlap said fuse layer; forming a first insulating layer having a first relative dielectric constant and constituting a part of a passivation layer to cover said bonding pad layer and said interlayer insulating layer; forming, in said first insulating layer, a first opening with a first opening width (W1) penetrating said first insulating layer located directly above said fuse layer, and a second opening penetrating said first insulating layer to selectively expose a surface of said bonding pad layer, and forming a concave portion having sidewalls connected to sidewalls of said first opening and a bottom surface in said interlayer insulating layer on a surface of said interlayer insulating layer; forming a second insulating layer having a second relative dielectric constant higher than said first relative dielectric constant and constituting a portion of said passivation layer on said first insulating layer to cover said first and second openings and said concave portion; forming a mask layer on said second insulating layer, provided with a third opening with a second opening width (W2) smaller than said first opening width (W1) directly above said fuse layer, and provided with a fourth opening on said second opening; and forming a fifth opening exposing a bottom surface of said concave portion located directly above said fuse layer, and a sixth opening selectively exposing the surface of said bonding pad layer by etching said second insulating layer using said mask layer as a mask.

Claim 6

A method of manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating layer on a substrate; forming a bonding pad layer on a surface of said interlayer insulating layer; forming a first insulating layer with a first relative dielectric constant to cover said bonding pad layer, constituting a portion of a passivation layer; forming a first opening with a first opening width exposing a surface of said bonding pad layer in said first insulating layer, by selectively etching said first insulating layer; forming a second insulating layer with a second relative dielectric constant higher than said first relative dielectric constant on said first insulating layer to cover said first opening, constituting a portion of said passivation layer; forming a mask layer provided with a second opening with a second opening width smaller than said first opening width directly above said first opening; and forming a third opening which exposes a portion of said bonding pad layer by etching said second insulating layer using said mask layer as a mask, and covering sidewalls of said first opening with said second insulating layer.

Claim 7

A method of manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating layer on a substrate; forming a bonding pad layer on a surface of said interlayer insulating layer; forming a first insulating layer with a first relative dielectric constant to cover said bonding pad layer, constituting a portion of a passivation layer; forming a first opening with a first opening width exposing a surface of said bonding pad layer in said first insulating layer, by selectively etching said first insulating layer; forming a second insulating layer with a second relative dielectric constant higher than said first relative dielectric constant on said first insulating layer to cover said first opening, constituting a portion of said passivation layer; forming a mask layer provided with a second opening with a second opening width smaller than said first opening width directly above said first opening; and forming a third opening which exposes a portion of said bonding pad layer by etching said second insulating layer using said mask layer as a mask, and covering sidewalls of said first opening with said second insulating layer.