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Patent US6004619A successfully refreshed from Google Patents.
US6004619A
Expired / Lapsed
US
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Process for manufacturing printed circuit boards
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1997-11-07
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Granted: 1999-12-21
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Expires: 2017-11-07
Abstract
Abstract Process for manufacturing circuit boards in which a masking layer (2) is applied to a carrier substrate (1) of insulating material and after producing openings for soldering pads, conductor traces, and through or blind holes, in accordance with a preferred embodiment by laser ablation, a thin electrically conductive layer (5) is applied to the surface of the carrier substrate including the masking layer. Subsequently, the masking layer (2) and the conductive layer deposited thereon, for example copper, are removed and the remaining metal surfaces (6) are chemically reinforced to produce the desired thickness. The process permits the production of dense structures using few process steps and without additional abrasion steps.
Inventors
- 👤 Siegfrid Dippon
- 👤 Walter Olbrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:31
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/10; H05K3/14; H05K3/143; H05K3/107; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/6565; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0376; H05K2201/09; H05K2201/09009; H05K2201/09036; H05K3/0011; H05K3/0017; H05K3/0026; H05K3/0032; H05K3/02; H05K3/04; H05K3/046; H05K3/048; H05K3/146; H05K3/38; H05K3/388; H05K3/40; H05K3/42; H05K3/425; H05K3/426; H05K3/428; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
149 words
Process of manufacturing printed circuit boards, comprising the following steps: a) applying a masking layer to an insulating carrier substrate, b) then producing recesses in the masking layer and in an upper region of the carrier substrate for at least one of (i) soldering pads, (ii) conductor traces and (iii) through holes in the masking layer and the carrier substrate, c) then applying a conductive layer to the surface of the carrier substrate while the masking layer is in situ on the carrier substrate so that the conductive layer is applied to the masking layer and recesses, d) then removing the masking layer with the conductive layer applied thereon without removing the conductive layer from the recesses so that a residual portion of the conductive layer remains in the recesses, and e) then applying metal to the residual portion of the conductive layer to attain a thicker residual portion.
Claim 2
Dependent Claim
149 words
Process of manufacturing printed circuit boards, comprising the following steps: a) applying a masking layer to an insulating carrier substrate, b) then producing recesses in the masking layer and in an upper region of the carrier substrate for at least one of (i) soldering pads, (ii) conductor traces and (iii) through holes in the masking layer and the carrier substrate, c) then applying a conductive layer to the surface of the carrier substrate while the masking layer is in situ on the carrier substrate so that the conductive layer is applied to the masking layer and recesses, d) then removing the masking layer with the conductive layer applied thereon without removing the conductive layer from the recesses so that a residual portion of the conductive layer remains in the recesses, and e) then applying metal to the residual portion of the conductive layer to attain a thicker residual portion.
Claim 3
Dependent Claim
49 words
Process in accordance with claim 1, characterized in that, to produce a multi-layer circuit board, a carrier substrate is laminated onto at least one side of a standard circuit board or the circuit board produced in accordance with claim 1, and process steps a) through e) are carried out.
Claim 4
Dependent Claim
17 words
Process in accordance with claim 1, characterized in that the recessed structures are produced by laser ablation.
Claim 5
Dependent Claim
31 words
Process in accordance with claim 1, characterized in that the recesses in the upper region of the carrier substrate in accordance with step b) have a depth of approximately 20 μm.
Claim 6
Dependent Claim
26 words
Process in accordance with claim 1, characterized in that application of the conductive layer is performed by physical vapor deposition or plasma enhanced vapor deposition processes.
Claim 7
Dependent Claim
17 words
Process in accordance with claim 2, characterized in that the recessed structures are produced by laser ablation.
Claim 8
Dependent Claim
29 words
Process in accordance with claim 6, characterized in that the structure depth in the upper region of the carrier substrate in accordance with step b) is approximately 20 μm.
Claim 9
Dependent Claim
26 words
Process in accordance with claim 7, characterized in that application of the conductive layer is performed by physical vapor deposition or plasma enhanced vapor deposition processes.
Claim 10
Dependent Claim
61 words
Process in accordance with claim 1, wherein the conductive layer is applied, the masking layer is removed and the metal is applied to the residual portion of the conductive layer so that all exposed portions of the soldering pads of through holes and the conductor traces remaining on the carrier substrate after the masking layer has been removed are substantially coplanar.
References Cited (Backward Citations)
EP0260514A1
Cited
EP0677985A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |