Method of forming connection hole

Claim 1

A method for making a connection hole, comprising the steps of: providing a silicon substrate having a surface including a pair of spaced apart electrodes, each electrode including a lower gate oxide film layer disposed on said surface and an upper gate electrode disposed on said lower gate oxide film layer, upper and side surfaces of each electrode being covered by an offset oxide film and sidewall, respectively, said substrate further including source and drain regions having an LDD structure defined in the substrate adjacent said electrodes; depositing an etching stopper film comprising an SiN based material on said offset oxide film, said sidewalls and any remaining exposed portions of said substrate surface; depositing an interlayer insulating film comprising an SiO x based material on said etching stopper film; depositing an organic film on said interlayer insulating film and patterning the organic film to define a connection hole pattern between said electrodes; anisotropically etching said interlayer insulating film using the organic film as a mask by plasma processing in an ECR oxide film etcher with a fluorocarbon (FC)-based gas to selectively remove portions of the interlayer insulating film to partially define a connection hole and simultaneously deposit an FC based protective film only on said etching stopper film; removing said FC based protective film by only oxygen plasma processing in an asher; and thereafter, removing portions of said etching stopper film by plasma processing in an ECR polysilicon film etcher with a fluorocarbon based gas to provide an anisotropically selectively etched connection hole extending through said interlayer insulating film and said etching stopper layer to an exposed surface portion of said substrate surface.

Claim 2

A method for making a connection hole, comprising the steps of: providing a silicon substrate having a surface including a pair of spaced apart electrodes, each electrode including a lower gate oxide film layer disposed on said surface and an upper gate electrode disposed on said lower gate oxide film layer, upper and side surfaces of each electrode being covered by an offset oxide film and sidewall, respectively, said substrate further including source and drain regions having an LDD structure defined in the substrate adjacent said electrodes; depositing an etching stopper film comprising an SiN based material on said offset oxide film, said sidewalls and any remaining exposed portions of said substrate surface; depositing an interlayer insulating film comprising an SiO x based material on said etching stopper film; depositing an organic film on said interlayer insulating film and patterning the organic film to define a connection hole pattern between said electrodes; anisotropically etching said interlayer insulating film using the organic film as a mask by plasma processing in an ECR oxide film etcher with a fluorocarbon (FC)-based gas to selectively remove portions of the interlayer insulating film to partially define a connection hole and simultaneously deposit an FC based protective film only on said etching stopper film; removing said FC based protective film by only oxygen plasma processing in an asher; and thereafter, removing portions of said etching stopper film by plasma processing in an ECR polysilicon film etcher with a fluorocarbon based gas to provide an anisotropically selectively etched connection hole extending through said interlayer insulating film and said etching stopper layer to an exposed surface portion of said substrate surface.