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US5995167A
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Apparatus for controlling display memory for storing decoded picture data to be displayed and method thereof
Assignee: Toshiba Corp
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Filing: 1997-11-05
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Granted: 1999-11-30
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Expires: 2017-11-05
Abstract
Abstract An apparatus for controlling a display memory for storing decoded picture data is disclosed, that comprises a data dividing portion for dividing decoded picture data as one macroblock in a vertical direction, a write address generator for generating the binary value of a write address necessary for writing the divided picture data to the display memory, a slice counter for counting the number of slice lines of picture data that has been written to the display memory, a rotate-shifter for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted, a means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted, a read address generator for generating the binary value of a read address necessary to read picture data from the display memory, a rotate-shifter for rotating and shifting the binary value of the generated read address to the left by a second bit number corresponding to output data of the slice counter, and a means for reading picture data from the display memory corresponding to the read address that has been rotated and shifted.
Inventors
- 👤 Michihiro Fukushima
- 👤 Shuji Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:01
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; G; G09; G09G; G09G5/00; G09G5/42; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N19/60; H04N19/61
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
200 words
An apparatus for controlling a display memory for storing decoded picture data as one macroblock, comprising: dividing means for dividing decoded picture data as one macroblock in a vertical direction; write address generating means for generating the binary value of a write address necessary for writing the divided picture data to the display memory; means for counting the number of slice lines of picture data that has been written to the display memory; first shifting means for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted; means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted; read address generating means for generating the binary value of a read address necessary to read picture data from the display memory; second shifting means for rotating and shifting the binary value of the generated read address to the left by a second bit number corresponding to output data of said counting means; and means for reading picture data from the display memory corresponding to the read address that has been rotated and shifted.
Claim 2
Independent Claim
200 words
An apparatus for controlling a display memory for storing decoded picture data as one macroblock, comprising: dividing means for dividing decoded picture data as one macroblock in a vertical direction; write address generating means for generating the binary value of a write address necessary for writing the divided picture data to the display memory; means for counting the number of slice lines of picture data that has been written to the display memory; first shifting means for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted; means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted; read address generating means for generating the binary value of a read address necessary to read picture data from the display memory; second shifting means for rotating and shifting the binary value of the generated read address to the left by a second bit number corresponding to output data of said counting means; and means for reading picture data from the display memory corresponding to the read address that has been rotated and shifted.
Claim 3
Dependent Claim
110 words
The apparatus as set forth in claim 1, wherein said dividing means divides the picture data decoded as one macroblock into 2 n pixels in the vertical direction of the macroblock, wherein said first shifting means rotates and shifts the binary value of the generated write address to the left by a first bit number of which the counted slice line number is multiplied by "n", and wherein said second shifting means rotates and shifts the binary value of the generated read address to the left by a second bit number of which a value of which "1" is subtracted from the counted slice line number is multiplied by "n".
Claim 4
Dependent Claim
32 words
The apparatus as set forth in claim 1, wherein said write address generating means successively generates binary values of write addresses that increment from "0" by "1" from the start slice line.
Claim 5
Dependent Claim
74 words
The apparatus as set forth in claim 1, wherein said read address generating means successively generates binary values of read addresses that increment from "0" by "1" as the start address of a line to be read whenever the line to be read is changed and successively generates binary values of read addresses that increment from the binary value of the start read address of the line to be read by "2 n ".
Claim 6
Independent Claim
169 words
A method for controlling a display memory for storing decoded picture data as one macroblock, comprising the steps of: dividing decoded picture data as one macroblock in a vertical direction; generating the binary value of a write address necessary for writing the divided picture data to the display memory; rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted; writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted; generating the binary value of a read address necessary to read picture data from the display memory; rotating and shifting the binary value of the generated read address to the left by a second bit number corresponding to the number of splice lines of picture data that has been written to the display memory; and reading picture data from the display memory corresponding to the read address that has been rotated and shifted.
Claim 7
Independent Claim
169 words
A method for controlling a display memory for storing decoded picture data as one macroblock, comprising the steps of: dividing decoded picture data as one macroblock in a vertical direction; generating the binary value of a write address necessary for writing the divided picture data to the display memory; rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted; writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted; generating the binary value of a read address necessary to read picture data from the display memory; rotating and shifting the binary value of the generated read address to the left by a second bit number corresponding to the number of splice lines of picture data that has been written to the display memory; and reading picture data from the display memory corresponding to the read address that has been rotated and shifted.
Claim 8
Dependent Claim
132 words
The method as set forth in claim 5, wherein the dividing step is performed by dividing the picture data decoded as one macroblock into 2 n pixels in the vertical direction of the macroblock, wherein the first shifting step is performed by rotating and shifting the binary value of the generated write address to the left by bits corresponding to a value of which the number of slice lines of picture data that has been written is multiplied by "n", and wherein the second shifting step is performed by rotating and shifting the binary value of the generated read address to the left by bits corresponding to a value of which "1" is subtracted from the number of slice lines that have been written to the display memory is multiplied by "n".
Claim 9
Dependent Claim
35 words
The method as set forth in claim 5, wherein the write address generating step is performed by successively generating binary values of write addresses that increment from "0" by "1" from the start slice line.
Claim 10
Dependent Claim
77 words
The method as set forth in claim 5, wherein the read address generating step is performed by successively generating binary values of read addresses that increment from "0" by "1" as the start address of a line to be read whenever the line to be read is changed and successively generating binary values of read addresses that increment from the binary value of the start read address of the line to be read by "1 n ".
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |