EP0503956A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Decompression of video signal
Assignee: LSI Corp
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Filing: 1992-03-13
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Granted: —
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Expires: 2012-03-13
Abstract
Abstract A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the present invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the present invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the present invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors. The 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel X 2 pixel "quad pixel" configuration, or in a 4 pixel X 1 pixel horizontal "scan" configuration. A structure including four of the decompression structures and a method are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, each decompression structure decodes a 480 X 1088-pixel picture area with access to up to two additional 240 X 1088-pixel picture area. A method using a divide-by-15 divisor is provided in the HDTV decompression structure to map the display space into the external DRAM with efficient use of the DRAM physical address space.
Inventors
- 👤 Steven C. Purcell
- 👤 David E. Galbi
- 👤 Frank H. Liao
- 👤 Yvonne C. Tse
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 04:04
CPC Classifications
H; H04; H04N; H04N19/00; G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G10; G10L; G10L19/00; G10L19/02; H03; H03M; H03M7/00; H03M7/30; H03M7/40; H03M7/42; H03M7/425; H04N19/10; H04N19/102; H04N19/124; H04N19/126; H04N19/42; H04N19/423; H04N19/43; H04N19/433; H04N19/436; H04N19/439; H04N19/44; H04N19/60; H04N19/61; H04N19/63; H04N19/90; H04N21/00; H04N21/40; H04N21/41; H04N21/426; H04N5/00; H04N5/44; H04N5/60; H04N5/602; H04N5/76; H04N5/907; H04N7/00; H04N7/015; G09G2340/00; G09G2340/02; G10L19/005; H04N19/70; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 60
Claim 1
Independent Claim
99 words
An apparatus for decompressing coded compressed video signal, comprising: means for retrieving from memory compressed video signals and for providing the compressed video signals on a bus; means for decoding compressed video signals received from the bus, and for providing the decoded video signals on the bus; means for receiving from the bus the decoded video signals, for performing an inverse discrete cosine transform on the decoded video signals, and for providing the transformed video signals on the bus; means for receiving from the bus the transformed video signals, for providing the transformed video signals as output data signals.
Claim 2
Dependent Claim
27 words
An apparatus as claimed in claim 1 wherein the memory retrieving means, the decoding means, the transforming means and the output means are controlled by a processor.
Claim 3
Dependent Claim
29 words
An apparatus as claimed in claim 2 wherein the memory retrieving means, the decoding means and the transforming means each have control and data register accessed by the processor.
Claim 4
Dependent Claim
62 words
An apparatus as claimed in claim 1, 2 or 3 wherein the memory retrieving means comprises: means for receiving the coded compressed video signals from an external source and for providing the coded compressed video signals on the bus; and means for receiving the coded compressed video signals from the bus and for storing the coded compressed video signals in the memory.
Claim 5
Dependent Claim
35 words
An apparatus as claimed in claim 1, 2, 3 or 4 wherein the coded compressed video signals are both interframe and intraframe coded, and the decoding means provides motion vectors for reconstructing interframe coded pictures.
Claim 6
Dependent Claim
21 words
An apparatus as claimed in claim 5 comprising means for receiving the motion vectors and for reconstructing the interframe coded pictures.
Claim 7
Independent Claim
18 words
An apparatus as claimed in any preceding claim comprising a host bus for communication with a host computer.
Claim 8
Independent Claim
93 words
A method of decompressing a coded compressed video signal comprising the steps of: retrieving from a memory compressed video signals and providing the compressed video signals on a bus; decoding compressed video signals received from the bus, and providing the decoded video signals on the bus; receiving from the bus the decoded video signals, performing an inverse discrete cosine transform on the decoded video signals, and providing the transformed video signals on the bus; and receiving from the bus the transformed video signals for providing the transformed video signals as output data signals.
Claim 9
Dependent Claim
26 words
A method as claimed in claim 8 comprising controlling the memory retrieving means, the decoding means, the transforming means and the output means by a processor.
Claim 10
Dependent Claim
35 words
A method as claimed in claim 9 wherein the retrieval from the memory step, the decoding step and the transforming step are performed by means each having control and data registers accessed by said processor.
Claim 11
Dependent Claim
58 words
A method as claimed in claim 9 or 10 wherein the memory retrieval step comprises the steps of: receiving the coded compressed video signals from an external source and providing the coded compressed video signals on the bus; and receiving the coded compressed video signals from the bus and storing the coded compressed video signals in the memory.
Claim 12
Dependent Claim
35 words
A method as claimed in claim 9, 10 or 11 wherein the coded compressed video signals are both interframe and intraframe coded, and the decoding step comprises providing motion vectors for reconstructing interframe coded pictures.
Claim 13
Dependent Claim
21 words
A method as claimed in claim 12 comprising the step of receiving the motion vectors and reconstructing the interframe coded pictures.
Claim 14
Independent Claim
24 words
A method as claimed in any one of claims 9-13 comprising the step of providing a host bus for communication with a host computer.
Claim 15
Independent Claim
124 words
A method of mapping a 2-dimensional space represented by x and y vectors (x, y) into a linear address space of a paged memory system, comprising the steps of: dividing the binary representation of the vector x into higher order bits xh and lower order bits xl; dividing the binary representation of the vector y into higher order bits yh and lower order bits yl, such that the number of memory addresses representable by combining the bits of xl and yl is less than a page of the memory; and providing as memory address of the paged memory system an address having higher order bits derived from the xh and yh bits and having lower order bits derived from the xl and yl bits.
Claim 16
Dependent Claim
43 words
A method as claimed in claim 15 wherein the 2-dimensional space is a video display space and the number of addresses representable by combining the bits xl and yl is not less than the number of pixels in a macroblock of video data.
Claim 17
Independent Claim
136 words
A method of mapping a 2-dimensional space represented by x and y vectors (x, y) into a linear address space of a paged memory system, said paged memory system being organized into words, each word having individually addressable first and second portions, said method comprising the steps of: designating a bit yu in the binary representation of vector y; designating a bit xe in the binary representation of vector x; and mapping into (i) memory addresses of said first portion vectors having the values of xe and yu being respectively 1 and 0, and vectors having the values of xe and yu being 0 and 1, and (ii) memory addresses of said second portion vectors having the values of xe and yu being both 1, and vectors having the values of xe and yu both 0.
Claim 18
Dependent Claim
60 words
A method as claimed in claim 17 wherein the paged memory system is addressable in one of first and second modes, wherein in the first mode, the first and second portions have memory addresses differing only in the yu bit, and wherein in the second mode, the first and second portions have memory addresses differing only in the xe bit.
Claim 19
Independent Claim
95 words
A method of mapping a 2-dimensional display space addressable by vectors X, Y onto a linear physical address space of a memory system, comprising the steps of: dividing the bits of the X vector into higher order vector Xh and lower order vector Xl; dividing arithmetically the Xl vector by an integer 2 n -1, n being an integer, to obtain a quotient and a reminder between 0 and 2 n -2; combining the bits of the vector Xh, the vector Y, the quotient and the remainder to form an address in the address space.
Claim 20
Dependent Claim
130 words
A method as claimed in claim 19 wherein the combining step comprises the steps of: testing the magnitude of the Y vector; combining, when the Y vector is less than a predetermined value, the bits of the vector Xh, the vector Y, the quotient and the remainder to form an address in the address space, and carrying out, when the Y vector is not less than the predetermined value, the steps of: dividing the bits of the vector Y into higher order vector Yh and lower order vector Yl, the vector Yh being the same number of bits as the vector Xl; and combining the bits of the vector Yl, the vector Xh, the quotient,the reminder and the value 2 n -1 to form an address in the address space.
Claim 21
Independent Claim
127 words
An apparatus for mapping a 2-dimensional space represented by x and y vectors (x, y) into a linear address space of a paged memory system, comprising: means for dividing the binary representation of the vector x into higher order bits xh and lower order bits xl; means for dividing the binary representation of the vector y into higher order bits uh and lower order bits yl, such that the number of memory addresses representable by combining the bits of xl and yl is less than a page of said memory; and means for providing as memory address of said paged memory system an address having higher order bits derived from said xh and yh bits and having lower order bits derived from said xl and yl bits.
Claim 22
Dependent Claim
43 words
An apparatus as claimed in claim 21, wherein the 2-dimensional space is a video display space and the number of addresses representable by combining the bits xl and yl is not less than the number of pixels in a macroblock of video data.
Claim 23
Independent Claim
139 words
An apparatus for mapping a 2-dimensional space represented by x and y vectors (x, y) into a linear address space of a paged memory system, the paged memory system being organized into words, each word having individually addressable first and second portions, the apparatus comprising: means for designating a bit yu in the binary representation of vector y; means for designating a bit xe in the binary representation of vector x; and means for mapping into (i) memory addresses of said first portion vectors having the values of xe and yu being respectively 1 and 0, and vectors having the values of xe and yu being 0 and 1, and (ii) memory addresses of the second portion vectors having the values of xe and yu being both 1, and vectors having the values of xe and yu both 0.
Claim 24
Dependent Claim
62 words
An apparatus as claimed in claim 23 wherein the paged memory system is addressable in one of first and second modes, wherein in the first mode, the first and the second portions have memory addresses differing only in the yu bit, and wherein in the second mode, the first and the second portions have memory addresses differing only in the xe bit.
Claim 25
Independent Claim
98 words
An apparatus for mapping a 2-dimensional display space addressable by vectors X, Y onto a linear physical address space of a memory system, comprising: means for dividing the bits of the X vector into higher order vector Xh and lower order vector Xl; means for dividing arithmetically the Xl vector by an integer 2 n -1, n being an integer, to obtain a quotient and a remainder between 0 and 2 n -2; means for combining the bits of the vector Xh, the vector Y, the quotient and the remainder to form an address in the address space.
Claim 26
Dependent Claim
130 words
An apparatus as claimed in claim 25 wherein the combining means comprises: means for testing the magnitude of the Y vector; means for combining, when the Y vector is less than a predetermined value, the bits of the vector Xh, the vector Y, the quotient and the remainder to form an address in the address space; means for, when the Y vector is not less than the predetermined value, dividing the bits of the vector Y into higher order vector Yh and lower order vector Yl, the vector Yh being the same number of bits as the vector Xl; and means for combining the bits of the vector YI, the vector Xh, the quotient, the remainder and the value 2 n -1 to form an address in the address space.
Claim 27
Independent Claim
66 words
An apparatus for processing a picture area of m x n pixels, comprising: 2r memory banks, each memory bank storing the values of pixels in one non-overlapping group of m/2r X n pixels in said picture area; and r processors each capable of accessing a four of the 2r memory banks and being responsible for processing the pixels associated with two of said four memory banks.
Claim 28
Dependent Claim
96 words
An apparatus as claimed in claim 27 wherein each processor is associated with two neighboring processors, each neighboring processors being one of the r processors, the four memory banks being associated with a contiguous picture area of 2m/r X n pixels, the processor being responsible for processing the pixels in the two memory banks associated with the middle portion of said 2m/4 X n pixels picture area, and the neighboring processors being each responsible for processing one of the two groups of m/2r X n pixels on each side of the 2m/r X n picture area.
Claim 29
Dependent Claim
21 words
An apparatus as claimed in claim 27 or 28 wherein the r processors each process the contiguous picture area in lockstep.
Claim 30
Dependent Claim
43 words
An apparatus as claimed in claim 29 wherein each contiguous picture area is divided into an equal number of fixed-size picture areas, each processor further comprising means for ensuring that the time required for accessing each of the fixed-size areas is substantially constant.
Claim 31
Independent Claim
71 words
A method of processing a picture area of m x n pixels, comprising the steps of: providing 2r memory banks, each memory bank storing the values of pixels in one non-overlapping group of m/2r X n pixels in said picture area; and providing r processors each capable of accessing four of the 2r memory banks, said processor being responsible for processing the pixels associated with two of said four memory banks.
Claim 32
Dependent Claim
104 words
A method as claimed in claim 31 wherein the processor providing step further comprises the step of associating each processor with two neighboring processors, each neighboring processors being one of said r processors, said four memory banks being associated with a contiguous picture area of 2m/r X n pixels, said processor being responsible for processing the pixels in the two memory banks associated with the middle portion of said 2m/r X n pixels picture area, and said neighboring processors being each responsible for processing one of the two groups of m/2r X n pixels on each side of said 2m/r X n picture area.
Claim 33
Dependent Claim
26 words
A method as claimed in claim 31 or 32 comprising the step of ensuring that the r processors each process the contiguous picture area in lockstep.
Claim 34
Dependent Claim
44 words
A method as claimed in claim 33 wherein each contiguous picture area is divided into an equal number of fixed-size picture areas, said method further comprising the step of ensuring that the time required for accessing each of said fixed-size areas is substantially constant.
Claim 35
Independent Claim
130 words
An apparatus for decoding variable length codes embedding in a bit stream, each variable code being of one of a plurality of code types, said structure comprising: means for extracting from said bit stream a string of bits; a plurality of logic circuits each associated with one code type for receiving said string of bits, for decoding a variable length code from said string of bits, and for providing the length of said variable length code decoded and a decoded datum; means for identifying a code type in accordance with a syntax state machine; means for selecting one datum from said decoded data in accordance with said code type identified; and means for advancing the bit stream the number of bits equal in the length of the variable code decoded.
Claim 36
Independent Claim
126 words
A method of decoding variable length codes embedding in a bit stream, each variable code being of one of a plurality of code types, the method comprising the steps of: extracting from the bit stream a string of bits; providing a plurality of logic circuits each associated with one code type for receiving said string of bits, for decoding a variable length code form said string of bits, and for providing the length of said variable length code decoded and a decoded datum; identifying a code type in accordance with a syntax state machine; selecting one datum from said decoded data in accordance with said code type identified; and advancing the bit stream the number of bits equal to the length of the variable code decoded.
Claim 37
Independent Claim
109 words
An apparatus for computing the expression a + b * c using an accumulator, comprising: means for expressing c into a ternary (1, 0, -1) representation having digits d n-1 , ..., d₂, d₁ and d₀; means for computing the multiples of b having the form b*3 i , where i = 0,1,2,...n-1 and storing each multiple of b in a register; and means for adding to said accumulator, for each i, where i=0,1,2,...,n-1, the content of the register corresponding to b*3 i , when d i = 1, the value 0 when d i = 0, and the negated value of the register corresponding to b*3 i .
Claim 38
Dependent Claim
63 words
An apparatus as claimed in claim 37 wherein the expression computes a memory address under index mode, said apparatus further comprising means for adding to said accumulator a value a being the content of one of first and second registers selected in accordance with a signal indicating whether the sum of the content of said first register and b*c exceeds a predetermined value.
Claim 39
Independent Claim
105 words
A method of computing the expression b * c using an accumulator, comprising the steps of: expressing c into a ternary (1, 0, -1) representation having digits d n-1 , ..., d₂, d₁ and d₀; computing the multiples of b having the form b+3 i , where i = 0,1,2,..., n-1 and storing each multiple of b in a register; and for each i, where i=0,1,2,...,n-1, adding to said accumulator the content of the register corresponding to b*3 i , when d i = 1, the value 0 when d i = 0, and the negated content of the register corresponding to b*3 i .
Claim 40
Dependent Claim
64 words
A method as claimed in claim 39 wherein the expression computes a memory address under index mode, said method further comprising the step of adding to said accumulator a value a being the content of one of first and second registers elected in accordance with a signal indicating whether the sum of the content of said first register and b*c exceeds a predetermined value.
Claim 41
Independent Claim
350 words
A method for reading and writing in place n² words into a memory containing 4n² words organized in a linear address space, comprising: writing the first n² words of said 4n² words into memory locations according to memory addresses generated by a counter, said memory address being initially a base address, incremented after each of said first n² words are written; reading said first n² words of said 4n² words from, and simultaneously writing the second n² words of said 4n² words into, memory locations according to memory addresses generated by a counter, said memory address being initially said base address, and subsequently obtained by: (a) rotating four bits of the content in said counter by one bit, (b) incrementing said rotated four bits by 1; and (c) rotating said four bits by one bit in the opposite direction as said rotation in (a); reading said second n² words of said 4n² words from, and simultaneously writing the third n² words of said 4n² words into, memory locations according to memory addresses generated by said counter, said memory address being initially said base address, and subsequently obtained by: (a) rotating four bits of the content in said counter by two bits, (b) incrementing said rotated four bits by 1; and (c) rotating said four bits by two bits in the opposite direction as said rotation in (a); reading said third n² words of said 4n² words from, and simultaneously writing the fourth n² words of said 4n² words into, memory locations according to memory addresses generated by aid counter, said memory address being initially said base address, and subsequently obtained by: (a) rotating said four bits of the content in said counter by three bits, (b) incrementing said rotated four bits by 1; and (c) rotating said four bits by three bits in the opposite direction as said rotation in (a); and reading said fourth n² of said 4n² words from memory locations according to the memory addressed generated by a counter incremented after each of said fourth n² words are written, said memory address being initially said base address.
Claim 42
Independent Claim
275 words
An apparatus for reading and writing in place n² words into a memory containing 4n² words organized in a linear address space, comprising: means for writing the first n² words of said 4n² words into memory locations according to the memory addresses generated by a counter, said memory address being initially a base address, incremented after each of said first n² words are written; means for reading said first n² words of said 4n² words from, and simultaneously writing the second n² words of said 4n² words into, memory locations according to memory addresses generated by a counter, said memory address being initially said base address, and subsequently obtained by: (a) rotating four bits of the content in said counter by one bit, (b) incrementing said rotated four bits by 1; and (c) rotating said four bits by one bit in the opposite direction as said rotation in (a); means for reading said second n² words of said 4n² words from, and simultaneously writing the third n² words of said 4n² words into, memory locations according to memory addresses generated by said counter, said memory address being initially said base address, and subsequently obtained by: (a) rotating four bits of the content in said counter by two bits, (b) incrementing said rotated four bits by 1; and (c) rotating said four bits by two bits in the opposite direction as said rotation in (a); means for reading said third n² words of said 4n² words from memory locations according to the memory addresses generated by a counter incremented after each of said fourth n² words are written, said memory address being initially said base address.
Claim 43
Independent Claim
80 words
An apparatus for providing motion compensation in interframe coded current video data, using motion vectors (x, y) coded with respect to reference video data, comprising: means for receiving said current video data; means for receiving said reference video data; a filter for resampling said video data in x and y directions; weighted adder for interpolating said reference video data and for summing said interpolated reference video data with decoded data; and a pixel memory for containing said summed video data.
Claim 44
Dependent Claim
30 words
An apparatus as claimed in claim 43 wherein said filter comprises: a 2-tap filter for resampling in the horizontal direction; and a 3-tap filter for resampling in the vertical direction.
Claim 45
Dependent Claim
55 words
An apparatus as claimed in claim 43 or 44 wherein said motion vector comprises first and second portions, said first portion being provided to said filter for resampling, said apparatus further comprising means for computing the sum of the screen locations of said current video data, offset by said second portion of said motion vector.
Claim 46
Independent Claim
81 words
A method of providing motion compensation in interframe coded current video data, using motion vectors (x, y) coded with respect to reference video data, comprising: receiving said current video data; receiving said reference video data; providing a filter for resampling said video data in x and y directions; providing a weighted adder for interpolating said reference video data and for summing said interpolated reference video data with said decoded data; and providing a pixel memory for containing said summed video data.
Claim 47
Dependent Claim
35 words
A method as claimed in claim 46 wherein said filter providing step further comprises: providing a 2-tap filter for resampling in the horizontal direction; and providing a 3-tap filter for resampling in the vertical direction.
Claim 48
Dependent Claim
63 words
A method as claimed in claim 46 or 47 wherein said motion vector comprises first and second portions, said first portion being provided to said filter for resampling, said apparatus further comprising means for computing the sum of the screen locations of said reference data and the screen locations of said current video data, offset by said second portion of said motion vector.
Claim 49
Independent Claim
141 words
An apparatus for performing bilinear interpolation of two values, said interpolation being of the form c = w*a + ((2 n ⁻¹) -w)*b, n being an integer and 0 ≦ w < 2 n ⁻¹, said apparatus comprising: means for generating signal w′[0:n-1] having value 2 n -1 when w = 2 n ⁻¹, and w otherwise; multiplexer M₀ having as input data said values a and b, said multiplexer M₁ selecting as output datum input datum a when w′[0] = 1 and input datum b otherwise; n-2 multiplexers M₂, M₃,...,and M n-1 , each having as input data said values a and b, multiplexers M i , i=2,...,n-1, selecting input datum when w′[i] is 1, and selecting input datum b otherwise, and providing as output datum said selected datum shifted by i-1 bits; and means for adding said selected data.
Claim 50
Independent Claim
173 words
A method of performing bilinear interpolation of two values, said interpolation being of the form c = w*a + ((2 n ⁻¹)- w)*b, n being an integer and 0 ≦ w < 2 n ⁻¹, said method comprising the steps of: generating signal w′[0:n-1] having value 2 n -1 when w = 2 n ⁻¹, and w otherwise; providing multiplexer M₀ having as input data said values a and b, said multiplexer M₁ selecting as output datum input datum a when w′[0] = 1 and input datum b otherwise; providing multiplexer M₁ having as input data said values a and b, said multiplexer M₁ selecting as output datum input datum a when w′[1] = 1 and input datum b otherwise; providing n-2 multiplexers M₂, M₃,..., and M n-1 , each having as input data said values a and b, multiplexers mi, i=2,...,n-1, selecting input datum a when w′[i] is 1, and selecting input datum b otherwise, and providing as output datum said selected datum shifted by i-1 bits; and adding said selected data.
Claim 51
Independent Claim
118 words
A method of processing elements column by column in an n X n matrix stored in first and second pages of a memory capable of page mode access, wherein said processing requires as input data two neighboring elements in the same column, said method comprising the steps of: processing said n X n matrix column by column, stopping in each column at the first element having an address in said second page and saving the last element in said column having an address in said first page; and processing said the elements of said n X n matrix in said second page column by column, beginning at each column said first element and using said saved last element.
Claim 52
Independent Claim
116 words
An apparatus for processing elements column by column in an n X n matrix stored in first and second pages of a memory capable of page mode access, wherein said processing requires as input data two neighboring elements in the same column, said method comprising: means for processing said n X n matrix column by column, stopping in each column at the first element having an address in said second page and saving the last element having an address in said first page; and means for processing said the elements of said n X n matrix in said second page column by column, beginning at each column said first element and using said saved last element.
Claim 53
Independent Claim
87 words
An apparatus for meeting CAS low and CAS high times in a dynamic random access memory using a clock signal, comprising: means for detecting a rising edge and a falling edge of said clock signal; and means for providing said CAS signal a rising edge transition substantially immediately when said detecting means detects said rising edge in said clock signal, and for providing said CAS signal a falling edge transition after a substantial delay when said detecting means detects a falling edge transition in said clock signal.
Claim 54
Dependent Claim
48 words
An apparatus as claimed in claim 53 wherein said CAS providing means comprises: a plurality of delay elements, each delay element providing a signal indicative of a transition in said clock signal after a delay; and multiplexer means for selecting the output signal of one said delay elements.
Claim 55
Dependent Claim
34 words
An apparatus as claimed in claim 53 wherein said CAS providing means keeps said CAS signal at logic low after said falling edge transition of said CAS signal for at least one clock period.
Claim 56
Independent Claim
83 words
A method of meeting CAS low and CAS high times in a dynamic random access memory using a clock signal, comprising the steps of: detecting a rising edge and a falling edge of said clock signal; and providing a rising edge transition in said CAS signal substantially immediately when said rising edge in said clock signal is detected, and providing a falling edge transition in said CAS signal after a substantial delay when said falling edge transition in said clock signal is detected.
Claim 57
Dependent Claim
50 words
A method as claimed in claim 56 wherein said CAS signal providing step comprises the steps of: providing a plurality of delay elements, each delay element providing a signal indicative of a transition in said clock signal after a delay; and selecting the output signal of one said delay elements.
Claim 58
Dependent Claim
40 words
A method as claimed in claim 57 wherein said CAS signal providing step further comprises the step of keeping said CAS signal at logic low after said falling edge transition of said CAS signal for at lest one clock period.
Claim 59
Independent Claim
62 words
An apparatus for receiving data from off-chip dynamic random access memory (DRAM), the DRAM receiving on an input terminal a CAS signal, comprising: means for detecting a logic state transition; an input pin connected to said detecting means and said CAS signal terminal of said DRAM; and means for receiving said data a predetermined period time after detecting said logic state transition.
Claim 60
Independent Claim
88 words
A method of accurately timing data arrival at an integrated circuit chip from an off-chip dynamic random access memory (DRAM), the DRAM receiving on an input terminal a CAS signal, the method comprising the steps of: providing means for detecting a logic state transition; providing an input pin connected to said detecting means; connecting said input pin with said CAS signal terminal of said DRAM; detecting a logic state transition on said CAS signal; and receiving said data a predetermined period time after detecting said logic state transition.
References Cited (Backward Citations)
US5018077A
Cited
US5253078A
Cited
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